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Unified Power Model (UPM) Working Group
The Unified Power Model Working Group was created to address the lack of system level IP block power models. UPM’s rich semantics facilitate easy and interoperable model exchange and meet the needs of three distinct groups of users: IP providers and model producers, system architects and SoC designers, and EDA developers. UPM has been formally standardized as IEEE 2416-2019.
Specification
- System Level Power Model Interface and Data Representation v3.0
Low Power Coalition
The Si2 Low Power Coalition developed standards and enabling materials to support low power design by taking a flow-centric view from ESL to GDSII. It defined and published the Common Power Format standard, which allows designers to clearly and concisely express power constraints and intent.
CPF Specifications
- The LPC Glossary provides a common language for implementing this standard
- CPF 2.1
- CPF 2.0 Parser (License Required)
- CPF 2.0 Tutorial
- CPF 1.1 Pocket Guide
- CPF/UPF Interoperability Guide V2.0
Design Guides
- Practical Guide to Low-Power Design: An in-depth walkthrough of power-conscious design using the CPF
- Si2 Power Closure Flow V1.0: A step-by-step presentation of the optimal design process for power-aware structures
Additional Specifications and Documents
- System-Level Power Analysis
- System-Level Power Model Interface & Data Representation
- High Level Power Modeling Requirements
Chip Package Co-Design (Open3D)
The Chip-Package Co-Design (CPC) Technical Advisory Board drew from a wide range of the supply chain, including fabless leaders, packaging/OSAT, foundries, and system / OEMs. CPC was also engaged by a number of experts from research and academic communities for their domain knowledge.
CPC TAB defined open standard interfaces and formats to enable interoperable 2.5D and 3D design flows, providing common interfaces without infringing on proprietary algorithms, products, or methodologies.
3D-IC Design Exchange Format Standards
- Chip-Package Interface Protocol V1.0 (PDN)
- Chip Thermal Interface Protocol V1.0 (Thermal Management)
- PathFinding Interface Protocol V1.0 (PathFinding)
Silicon Photonics Technical Advisory Board (SP TAB)
The SP TAB is an R&D industry service to extend the OpenAccess database for photonic designs enabling photonic-electronic design flows.
Specifications
- Open Matrices: The Si2 SPTAB OpenMatrices XSD standard describes the n-port scatter parameters (through the scattering matrix) for the linear frequency-domain behavior of optical devices, possibly for different operating points such as temperature and voltage.
OpenDFM Coalition
OpenDFM provides a common set of Design for Manufacturability parameters for a wide variety of physical verification and analysis tools, dramatically improving the interface between EDA vendors and silicon foundries.
Specifications
- OpenDFM Specification v2.3.0.4: OpenDFM is an open, high-level DRC language that can generate popular verification languages with no loss of accuracy or performance.
- Universal Layer Model Specification: Jointly developed by the OpenDFM and OpenPDK Coalitions, the Universal Layer Model standardizes the data model for drawn and derived layers. This specification standardizes layer operators and guarantees the expected results from ULM layer operations.
OpenPDK Coalition
The OpenPDK (Process Design Kit) Coalition was founded in 2010 to define a set of open standards allowing an OpenPDK to be created (once) and translated into specific EDA vendor tools and foundry formats. This allows for maximum portability across foundries and agnosticism among EDA tools. The Si2 OpenPDK standard enables greater efficiency in PDK development, verification, and delivery, providing equal support to foundries, EDA tool vendors, IP providers, and end-users.
Specifications
- OpenPDK Open Process Specification (OPS): This specification enables foundries to study and create electronic versions of DRM and to gather early feedback on completeness.
- OPS 1.2 supports the creation of a techfile/oaTech.db for foundry-specific layer information. This includes grids, connectivity, display information, and version information. This release also integrates the Device Parameters (previously called Design Parameters) and Tool Interface standards into OPS.
- OpenPDK PCell Standard (PCell v1.0 is compatible with OPS 1.2)
- OpenPDK Design Parameter and Callback Specification V1.0
- OpenPDK Schematic Symbol Standard V1.0
Design Guides
- ESD Protection Design Methodology V1.0: The design of Electro-Static Discharge protection devices in an integrated circuit should be evaluated and verified at all stages of a standard circuit design flow. A comprehensive set of ESD checks must be verified with appropriate tools to ensure the integrated circuit has robust ESD protection. This paper describes the ESD design flow, the various checking tools used at each level, and the technical requirements for each of these tools.
Open Modeling Coalition
The Open Modeling Calculation Interface (OMCI) developed by the Open Modeling Coalition provides standardized semantics for access to cell characterization data on the “model” side, and netlist information on the “design” side. The OMCI API is independent of any particular design database schema or modeling format syntax, providing run-time access to abstractions for those semantics. Support for any particular schema or format is accomplished via specialization of C++ classes at the OMCI source level.
Specifications
- OMCI Headers v1.0
- OMCI Reference Document v1.0
Effective Current Source Modeling Documents
- Liberty Extensions for Characterization and Validation v1.2.3.1
- ECSM Timing and Power Specification v2.1.2 (contributed by Cadence Design Systems) (ECSM License Required)
- ECSM Noise Specification v1.1 (contributed by Cadence Design Systems) (ECSM License Required)
- ECSM Characterization Guidelines
- ECSM Statistical Extensions Specification v1.3
Note that this work is unrelated to the Open Model Interface defined by the Compact Model Coalition, which can be found here.