Dr. Leigh Anne Clevenger Named Si2 Director, OpenStandards

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Silicon Integration Initiative has selected Dr. Leigh Anne Clevenger as director of OpenStandards, effective January 1, 2021. She will replace Jerry Frenkil, who has served in this role since 2015. Frenkil will remain with Si2 as an advisor to staff, board, and member companies on adoption of the IEEE 2416 Unified Power Modeling Standard.

Since joining Si2 in 2018, Clevenger has been the lead developer of the Si2 prototype power calculator, demonstrating the UPM/IEEE-2416 standard. She will continue to drive the UPM working group toward its goals of developing and adopting the standard. Additionally, leveraging her doctorate in Software She will continue to drive the UPM working group toward its goals of enhancement and adoption of the standard. and Machine Learning, Clevenger is currently spearheading the effort to identify and solve industry needs in applying artificial intelligence and machine learning to electronic design automation tools.

With this promotion, Clevenger will continue working directly with Si2 members and industry leaders to identify and solve issues in semiconductor design flow interoperability. As an R&D Joint Venture providing antitrust protection for its members, Si2 is uniquely positioned to organize collaborative efforts, with the ultimate goal of widespread adoption of standards providing EDA tool interoperability and customer data access.

“Starting the Special Interest Group on AI/ML in EDA served as Leigh Anne’s introduction to the role Si2 has as an R&D Joint Venture,” said John Ellis, president and CEO. “Through a series of interviews with Si2 member companies, she established a vision of the technical collaboration needed and the highest priority issues for the SIG to tackle.

“Leigh Anne has been a vital addition to our team. She added value to our operations from day one, applying her semiconductor experience to UPM coding. Following Si2’s growth path, we soon put her advanced AI/ML degree to use,” Ellis added. “The SIG she formed with industry experts is well on its way to closing some serious gaps found for effectively applying AI/ML to EDA. I look forward to what’s next for Leigh Anne. With her skills and drive, I expect great things.”

Clevenger, who earned her doctorate at Pace University, has published and presented research on data science including big data analytics, machine learning algorithms, and wearable computing. She brings to Si2 extensive experience in semiconductor design automation at IBM and semiconductor processing technology at GLOBALFOUNDRIES.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

Si2 Compact Model Coalition to Support CEA-Leti SPICE Simulation Model

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The Si2 Compact Model Coalition has announced the approval and financial support of L-UTSOI, a new ultra-thin, silicon-on-insulator transistor simulation model developed by CEA-Leti, a France-based research institute for electronics and information technologies.

L-UTSOI was selected for support by CMC, a coalition of 30 semiconductor companies that standardizes semiconductor models used in a class of circuit simulation tools called SPICE, or Simulation Program with Integration Circuit Emphasis. Manufacturers save time and money by simulating the performance of new or enhanced integrated circuit designs before the ICs are manufactured. The CMC funds leading universities and research institutions to develop, refine and maintain SPICE models, which are incorporated into widely used semiconductor design tools.

Silicon-on-insulator uses a thin layer of insulating oxide that semiconductor manufacturers insert between a silicon substrate and the top silicon layer. That insulating layer improves power efficiency and reliability. When compared with conventional bulk-silicon CMOS devices, SOI designs are well-suited for low-cost, low-power applications, such as automotive and the Internet of Things.

“CEA-Leti’s compact model boasts physically based model parameters,” said Harrison Lee, chair of the L-UTSOI Working Group and principal engineer of the Foundry Design Enablement Team at Samsung Electronics. “We can utilize predictive analysis of a process technology to optimize a transistor’s design implementation for a specific end-use. With a capability to 10 nanometers and below and the ability to simulate a wide range of voltages and body biases, we can easily research a wide variety of analog and digital applications.”

André Juge, working group co-chair and fellow member of technical staff at STMicroelectronics, stated, “L-UTSOI features accurate modeling of ultra-thin body and box fully-depleted SOI devices, combined with high predictiveness and numerical performance for simulation of circuits operating in a wide range of applications. For several years, starting at the 28-nanometer technology node and below, L-UTSOI has been a key enabler for design technology co-optimization.”

“CMC provides a rare opportunity to work in tandem with the simulator suppliers that are implementing our code, and the end-users which create the designs,” said Thierry Poiroux, head of the Simulation and Compact Modeling Laboratory at CEA-Leti. “Regular CMC meetings ensure a quick response to feature and bug-fix requests. We look forward to this same support from the CMC stakeholders implementing and using the L-UTSOI model.”

“As a member-driven organization, the CMC strives to provide value for its members and the semiconductor supply chain,” said Peter Lee, CMC chair. “With 15 models now available, CMC members have a distinct competitive advantage with early access to new features and bug fixes, and an 18-month lead on standard models released to the public. Adding L-UTSOI to the mix of models was a direct response to our customer request for model support, as we continue to add value to their membership. ”

IEEE Approves New Power Modeling Standard. 2416-2019 Built on Si2 Unified Power Model

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AUSTIN, Texas–Silicon Integration Initiative has announced that its Unified Power Model, developed with major contributions from IBM and GLOBALFOUNDRIES, has been approved as IEEE 2416-2019, a new Standard for Power Modeling to Enable System Level Analysis, which complements UPF/IEEE 1801-2018 Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems.

Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

UPM/IEEE 2416-2019 provides a rich set of power modeling semantics enabling system designers to model entire systems with great flexibility. It supports power modeling from abstract design description all the way to gate level implementation providing data consistency from earliest architectural explorations to final power verification.

“We view UPM/IEEE 2416 as a major step forward for low power design,” commented Dr. Nagu Dhanwada of IBM, chair of the IEEE 2416 and the Si2 UPM Working Groups.

“The foundation of the UPM/IEEE 2416-2019 standard originated in IBM and has been successfully used in power sign-off of several generations and families of IBM microprocessors. Concepts like multi-level, state-based modeling and efficient, expressive semantics in UPM/IEEE 2416-2019 support constructing accurate and standardized power models for IP blocks. This enables SoC designs to be energy efficient from the ground up, a key reason companies will use 2416-2019 to upgrade modeling, analysis and sign-off flows,” stated Dr. Dhanwada.

Si2 UPM is a product of the Si2 OpenStandards Coalition, an R&D incubator which rapidly seeds and prototypes potential new EDA software tool interoperability standards. “The target of this development and subsequent standardization was an efficient and flexible mechanism for the specification and interchange of consistent power models throughout a project’s lifetime, from system design to manufacturing, especially for IP blocks and chiplets,” said Jerry Frenkil, Si2 director of OpenStandards. “This work led to significant advances in power modeling, including contributor and multi-level modeling, both of which are included in the 2416-2019 standard.”

A prototype power tool, upmPowerCalc, was built to prove the new concepts from end-to-end, both accelerating the delivery of a ready-to-implement standard and providing OpenStandards members with tools to aid in their own implementation.” The Si2 work was supported by the UPM Working Group consisting of ANSYS, IBM, Intel, Cadence, Entasys, and Thrace Systems.

Power contributors are Process, Voltage, and Temperature independent proxies for power. This PVT independence enables the late binding of PVT conditions at simulation run time, enabling power analysis at various PVT corners without requiring new libraries. Multi-level models provide multiple model views, or interfaces, to access the same power data. With multi-level construction, a single model provides consistent data for both system-level abstract simulations and bit-level simulations with RTL or gates.

“These advancements, along with UPM’s semantic expressiveness, deliver multiple benefits for design organizations” Frenkil explained. “System architects and SoC designers can model entire systems at a variety of PVT points with great flexibility. Power can be modeled in UPM using scalars, tables, expressions, and contributors, as well as expressions referencing contributors.”

UPM’s expressiveness also provides major benefits for IP developers. The use of power contributors leads to significant productivity gains since far fewer models and libraries are needed with UPM’s PVT independence. In addition, the models are abstract black boxes – functionality cannot be reverse-engineered from the power models.

Model interoperability and consistency with UPF/IEEE 1801 were identified early on as key goals in support of increasing emphasis on system level design. “IEEE 2416 provides a standardized interoperable system-level power model that is an essential piece of the foundation of an emerging industry-scale chiplet ecosystem” commented Ramune Nagisetty, senior principal engineer and director of Process and Product Integration at Intel Corporation.

“Energy-aware, system-level design can be a challenging task,” added John Biggs, chair of the IEEE P1801 Working Group, and distinguished engineer and co-founder of Arm. “With this new standard, designers will be better enabled by having access to semiconductor IP delivered with both IEEE 1801 power state models and IEEE 2416 power data models.”

For design automation groups, UPM provides an industry-standard format for both internal and external IP. This common format saves resources and time as there is no need to support or translate external proprietary formats. UPM also reduces reliance on internal proprietary formats, a long-standing design obsolescence trap.

An EDA startup, Thrace Systems, is planning to add IEEE 2416 support to its products. “UPM/IEEE 2416 is an important new standard. Its rich modeling semantics provide our power analysis platform with the solid infrastructure needed for comprehensive system level analysis,” commented David Ratchkov, Thrace Systems founder and CEO.

The P2416 Working Group was led by IBM, Si2, and Cadence, with active support from Intel and Arm.

For more information contact Jerry Frenkil at [email protected].

Si2 Welcomes New Members: Mythic and Thrace Systems

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Si2 welcomes its newest members

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OpenAccess Coalition — Mythic
www.mythic-ai.com

 

 

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OpenStandards Coalition — Thrace Systems
www.thracesystems.com

IBM, GLOBALFOUNDRIES Enhance Si2 Unified Power Model Standard

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Si2 has announced  that IBM and GLOBALFOUNDRIES have contributed patented technology to support the Si2 Unified Power Model standard, the industry’s first significant power model enhancement in many years.

Early stage estimation of System on Chip power consumption is fundamental to ensuring new SoC designs meet or exceed power specifications when fabricated. For a credible estimate, the power models must comprehend the target implementation technology and circuitry, along with voltage and temperature conditions. At the same time, power estimation results are needed quickly in to perform rapid “what if” scenarios.

UPM’s multi-level power modeling capability provides the necessary level of modeling detail required at various stages of design. Abstract high-level equations to gate-level characterization tables can be accommodated through the same, standard interface. Beyond this, the UPM interface, upon acceptance and approval by the IEEE’s P2416 working group, will be a direct plug-in to the widely-used IEEE 1801 stub created for power models.

Simplified Power Modeling

The IBM and GF contributions enhance UPM by providing a new and unique approach to power modeling. Rather than storing pre-characterized, process-voltage-temperature specific data, UPM models store power proxies that represent different contributors to overall power consumption, such as sub-threshold leakage, gate leakage, and dynamic power. Appropriately entitled “power contributors,” this approach vastly simplifies and reduces the power modeling effort, and allows the power model to be voltage and temperature independent, enabling a single power model to be used at a multitude of voltages and temperatures.

SoC designers using UPM with contributor-based modeling will ultimately be equipped with thermally-aware, system-level power estimation. In addition, the late-binding of specific PVT conditions at simulation run-time will provide accurate, early estimates of leakage power, which increases exponentially with increasing temperature. The donated technology covers key aspects of contributor-based power modeling including model abstraction, generation, compression and evaluation.

Contributor-based modeling will be fully integrated into UPM, which forms the basis for P2416, the planned IEEE standard for developing and maintaining interoperable, IC design power models.  P2416 is scheduled for balloting in early 2019.

Industry Contributions

Jerry Frenkil, director of Si2 OpenStandards, said the IBM and GF contributions bolster UPM and provide P2416 with proven and ready-to-use modeling methods.  “These power proxies enable voltage and temperature-independent modeling which greatly reduce the model generation and support effort,” Frenkil explained. “They also enable late binding of voltage and temperature conditions at simulation run-time, a major benefit for both IP developers and SoC designers.”

“IBM is pleased to donate this advanced modeling technology to Si2’s UPM development to facilitate interchange of IP power data,” said Dr. Leon Stok, vice president of EDA at IBM.  “We have used contributor modeling internally on several generations of IBM micro-processors to great effect. We look forward to seeing UPM contributor models being provided by IP block developers so that entire systems, consisting of both internal and external IP, can be modeled efficiently using a common modeling standard.  Additionally, the combination of power contributors and multi-level modeling structures promises major cost and resource improvements in creating and supporting IP power models.”

“UPM directly addresses a major industry need—accurate and efficient system-level power models,” said Richard Trihy, senior director of design enablement at GF.  “Since IP providers need only produce a single model for a multitude of PVT points, these models enable significant productivity gains in model generation. Our clients will also get a good early estimate of their systems’ total power, including leakage, which can operate at high temperatures.”

Ready for P2416 Balloting

“These contributions from IBM and GF come at a fortuitous time,” said Dr. Nagu Dhanwada of IBM, chair of the IEEE P2416 Working Group and the Si2 UPM development project.  “The P2416 Working Group is rapidly gathering momentum towards IEEE standardization.  We anticipate going to ballot early next year.”

For more information about this project, contact Jerry Frenkil at [email protected].  For information about the Low Power Working Group and other OpenStandards programs, visit https://si2.org/openstandards/.

Si2 to Demonstrate System-Level Unified Power Model and Power Tool at DAC 2018

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Si2 to Demonstrate System-Level Unified Power Model and Power Tool at DAC 2018


New Standard and Prototype Tool Estimate and Control IC Power Consumption

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AUSTIN, Texas —Silicon Integration Initiative (Si2), an Austin-based integrated circuit research and development joint venture, will demonstrate its Unified Power Model (UPM), a newly developed system-level power modeling standard, and accompanying prototype tool at DAC 2018 in San Francisco. The Si2 standard and tool help designers estimate and control power consumption at the system level, abilities widely identified as critical requirements in meeting product power constraints.

Demonstrations will be held at the Moscone Center, Tuesday, June 26 and Wednesday, June 27, 11:00 a.m. and 2:00 p.m., Booth 1338.

UPM focuses on the system level and provides model consistency across different abstractions, from systems down to gates. Multiple data representations—expressions, multi-dimensional tables, and scalars—provide modeling flexibility. Voltage and temperature independent modeling greatly reduce the model generation and support effort, and enable the late binding of voltage and temperature conditions at simulation run-time.

“UPM is a flexible power modeling standard that facilitates interchange of IP power data, while providing several benefits like reduced model generation effort and costs, and enablement for early, accurate system level power estimates,” said Dr. Nagu Dhanwada of IBM, chair of the Si2 UPM project and the IEEE P2416 working group. UPM is the primary source for the emerging IEEE P2416 standard.

Jerry Frenkil, director of Si2 Open Standards, said UPM was developed to address low-power design issues at the system level. “For IP developers, the rich set of power modeling semantics supports IP macro abstraction and provides flexibility for a variety of modeling approaches.  For SoC designers, UPM’s temperature and voltage sensitive models enable thermally aware, system-level power estimation, vastly improving early analysis and quality of results,” Frenkil said.  “For EDA developers, UPM provides standardized compatibility with UPF/IEEE1801 and opportunities for new applications based upon UPM’s unique features.

“UPM has the additional benefit of industry and academic oversight, as the Si2 Low Power Working Group members—ANSYS, Cadence, Entasys, IBM, Intel and North Caroline State University (NCSU)—oversaw the development,” added Frenkil.  “NCSU’s involvement follows Si2’s long standing practice of partnering with Universities and Professors for collaborative R&D”.

The modeling language and prototype tool using that language, were developed in parallel.  Si2 designed and built a prototype system-level power estimator, PowerCalc, which natively uses the UPM IP models.  Additionally, PowerCalc was built from the ground up with support for multi-processing and cloud computing. This parallel development of the modeling standard and a compatible tool was a major factor in refining the model structure and enabling efficient model execution.

Si2 plans to contribute the latest UPM specification to the IEEE P2416 Standards Working Group for industry-wide standardization and distribution.  “Since Si2 is an R&D joint venture, our members can work together collaboratively, with anti-trust protection, to develop advanced technology, including specifications, prototypes, and reference designs.  Our work on UPM provides P2416 with a proven and ready to use model interface,” Frenkil added.

For more information about this project, contact Jerry Frenkil at [email protected].  For information about the Low Power Working Group and other OpenStandards programs, visit https://si2.org/openstandards/.

Founded in 1988, Si2 is a leading research and development joint ventures that provides standard interoperability solutions for integrated circuit design tools.  All Si2 activities are carried out under the auspices of the the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. Si2’s international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.

 

Contact

Terry Berke
512-917-1358
[email protected]

 

Si2 Launches Effort to Standardize New IC Design Language

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Silicon Integration Initiative Inc. (Si2), a research and development joint venture providing standard interoperability solutions for IC design tools, has launched a working group to standardize a new, formal declarative language that greatly simplifies finding and correcting design flaws in complex, leading-edge chip designs early in a design flow. Named OPAL (Open Pattern Analysis for Layout), […]

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New Si2 Working Group to Develop Unified Power Model for System-Level IC Design

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AUSTIN—Silicon Integration Initiative, Inc. (Si2), a research and development joint venture focused on integrated circuit design tool interoperability standards, has launched a System Level Power working group to create the Si2 Unified Power Model (UPM), a standard which will strengthen power management in system-level IC design.

Jerry Frenkil, director of the OpenStandards Coalition, which incubates new Si2 standards, said development of the Si2 UPM is part of the industry’s ongoing effort to improve energy and power efficiency throughout the system-on-a-chip development flow, with a focus on system design.

“Energy efficiency is a growing and costly constraint in integrated circuit design,” Frenkil explained.  “There’s currently no standard, single model to represent power data at the system level across a range of process, voltage, and temperature (PVT) points.  Different, often inconsistent models are currently used in each of the three major stages of IC design:  system design, register transfer level (RTL) design, and implementation.  None of those models currently support voltage or temperature dependencies.  The Si2 UPM addresses those issues.”

When completed, the Si2 UPM will enable faster turnaround time for system-level power and thermal analyses, as well as reduce resources and costs incurred in power model generation, Frenkil said.  The approved specification, including the capability to supply power data to IEEE 1801/UPF power state models, will be contributed to the IEEE P2416 Working Group for ongoing maintenance and industry-wide standardization. IEEE P2416 supports the ability to develop accurate, efficient and interoperable power models for complex, integrated circuit designs.

Si2 members participating in the working group are ANSYS (NASDAQ: ANNS), Cadence Design Systems (NASDAQ: CDNS), IBM (NYSE: IBM), Intel (NASDAQ: INTC) and Entasys.

The Si2 UPM will benefit the three major constituencies to the IC design ecosystem:

  • For IP providers:
    • A system-level power data model companion for the IEEE 1801 (UPF) power state model
    • reduced time and resources for model and library generation and support.
  • For system and SoC architects
    • true system-level modeling that eliminates the need for gate-level netlists.
    • faster turn-around time for system-level power and thermal analyses
    • model consistency across abstractions
  • For EDA providers
    • New, non-cannibalistic product and solution opportunities

For information about the new Si2 UPM working group or other Si2 OpenStandards projects, contact Jerry Frenkil, jfrenkil@si2.org.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust law.

Si2 Launches Effort to Improve IC Ecosystem

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Si2 Launches Effort to Improve IC Design Ecosystem

New Special Interest Group Will Present Recommendations at DAC 2018

Si2 is seeking industry input on an international effort to identify and address ways to streamline and improve the IC design ecosystem. The finished product will be a DAC 2018 white paper whose contents will present an industry consensus on specific ways the industry can manage the rising costs of more complex designs and smaller geometries.

Ted Paone, Si2 interoperability standards architect, said the first step in the process was the formation of the Si2 Design Ecosystem Special Interest Group (SIG), which will write and distribute an industry-wide survey identifying areas of concern. The survey will launch in March 2018. Intel, Cadence Design Systems, Micron, Samsung, IBM and PDF Solutions are charter members of the SIG, which will investigate the impact of current issues in design and the expectations of future design requirements including performance and interoperability improvements to design data bases and scripting languages.

IC designers and engineers can submit survey questions for consideration at https://www.surveymonkey.com/r/9NSZCLC.

“We’re asking for the industry to help identify their specific design concerns so we can incorporate them into our survey,” he explained. “These are the people whose day-to-day activities are complicated by the need to create successful silicon while dealing with more and more complex processes, larger designs, new security and traceability issues, and emerging technologies such as chiplets, photonic elements and three-dimensional packaging.”

For information about the Si2 Design Ecosystem SIG, contact Paone, [email protected].  Information about joining the SIG is available at www.si2.org.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust law.

Tom Whipple Elected Co-Chair of Si2 OpenStandards Technology Steering Group

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Tom Whipple, solutions architect at Zuken, has been elected co-chair of the Si2 OpenStandards Technology Steering Group. He joins co-chair Jerry Frenkil, director of OpenStandards, in this new leadership role.  Paul Stabler of IBM was elected secretary.

The Si2 OpenStandards membership offers the option for companies collaborate in one or all of a variety of  topical working groups that develop and approve standards for the global semiconductor industry. OpenStandards targets potential standards earlier, streamlines a path for more timely industry approval, and strengthens  inter-project collaboration. The TSG is responsible for coordinating OS technology roadmaps, and recommending formation of OS collaborating groups and monitoring their activities.

At Zuken, Tom is responsible for defining, promoting and supporting chip-package-board co-design solutions using Zuken CR-8000 design tools.