Si2 oaScript Symposium: Scripting Made Easy DAC 2017 Austin Convention Center, Room 7 Tuesday, June 20, 2017, 1:00 – 3:00 p.m. Can you easily write new applications for your users? We’ll show you how. Can you easily integrate script tools into your applications? We’ll show you how. Do your applications have a fast-track learning system? […]
Tom Whipple, solutions architect at Zuken, has been reelected chair of the Si2 Chip-Package Co-Design Technical Advisory Board. The TAB’s primary goal is to identify problems in chip-package-board design flows, and flows and data exchange solutions to solve them. At Zuken, Tom is responsible for defining, promoting and supporting chip-package-board co-design solutions using Zuken CR-8000 […]
– Si2 Contributes Advanced IC Power Modeling Technology to IEEE Technology will improve SoC design for power efficiency – AUSTIN, Texas–Silicon Integration Initiative, Inc. (Si2), a leading integrated circuit research and development joint venture, has contributed new power modeling technology to the IEEE P2416 System Level Power Model Working Group. The transfer is aimed at […]
By Marshall Tiner Director of Production Standards Si2 What is open about Si2 OpenAccess? It seems these days everything is “open,” and the terms get confusing. Here is a short history of a few key areas to help clarify things. The label “open source” is credited to the free software movement of 1998. […]
Paul Stabler, senior engineering manager in the IBM EDA organization, has been elected chairman of Si2 OpenAccess Coalition for 2017. He replaces Rudy Albachten of Intel, who assumes an advisory role as vice chairman. The OAC board oversees operational decisions for OpenAccess, the world’s most widely used, open-reference database with its own supporting standard API. […]
Nicolas Williams of Mentor Graphics has been elected to the Si2 Extensions Steering Group. The ESG determines which Si2 OpenAccess Coalition extensions become OAC working groups and move forward for possible industry standardization. At Mentor, Nicolas is responsible for specifying and leading product direction of Tanner tools for analog, RF and MEMS devices. He also […]
By Ted Paone Si2 Interoperability Standards Architect It is a new year but those design issues you could not fix last year are still robbing your company’s productivity. The problems didn’t stop at the beginning of this year, and there are less time and limited staff to find the solutions. […]
Jeshairaj Thakaria is the newest member of the Si2 University Partner Network. The network connects qualified engineering student-partners to their future employers in a program that offers real-world, electronic design automation job experience. A graduate student at the University of Florida Electrical and Computer Engineering Department, Jeshairaj is majoring in digital and mixed signal IC […]
The Si2 staff and board of directors welcome our newest members: Si2 OpenAccess Member INVECAS Santa Clara, Calif. Chengdu Higon Integrated Circuit Design Co., Ltd. China Intento Design Paris DXCorr Design, Inc. Sunnyvale, Calif. Si2 Base Member Savarti Company Limited Milpitas, Calif.
Good stories often start over a beer. While sharing a libation or n + 1 with several friends from the industry, one of them mentioned a problem with their fab supplied PDK. Another had a similar problem with a different PDK, by the end next round, I had collected a list of common problems that design groups were having with their PDKs.
A process design kit (PDK) models a specific fabrication process for a set of tools used in the design flow blessed by the fab. Using this PDK and following one of the fab supported design flows, the designers can create and verify a design that is manufacturable in that process. The PDKs available from the fabs not only reflect the specific manufacturing process but can be tailored for markets with the addition of processing steps and devices. This generic PDK works very well for many of the design groups. You can create a design and it can be manufactured.
With the competition in some markets, the design groups must take any advantage it can over its competitors. They choose the tools and methodologies specific to their design market and design style, these may deviate from the supported flows. These groups want to enhance the PDK to meet their needs. It isn’t just a drinking problem; these issues are industry wide. An industry wide problem can be solved with a collaboratively developed solution.
What You’ll Learn
In this tutorial, we will explore ways of customizing PDKs to support the tools and devices in your design flow without rewriting the existing PDKs. We will jump in with parameters, resetting defaults and other control and adding new parameters. On to PCells, customize the shapes, connectivity and properties without source code. Add new tools to the flow, integrating the technology and supporting new parameters and models. Integrate your own devices into the PDK and not have them overwritten on an uprev from the fab.
These solutions addressed many of the problems seen by the PDK Users. They represent what can be done by working collaboratively to solve common problems yet allowing each user to customize the implementation. Working together to address common issues, under the anti-trust protections provided by Si2 membership, SIG members create ideas, write white papers, conduct surveys, and develop prototypes; unique solutions sharing a common understanding of the problems.
The IEEE P2416 System Level Power Modeling Working Group will hold a face-to-face meeting at DAC on Monday, June 19, at 8:30 a.m. -10:30 a.m. Guests are welcome to attend and observe the proceedings. The agenda includes a discussion of recent power modeling contributions from Si2.
Recently donated to Si2 by Intel, OPAL is a high-level, layout modeling language for 2D pattern analysis. It is an object-orientated, declarative language that accurately describes a wide variety of problematic patterns known as hotspots. These patterns exhibit poor image transfer during lithography at 20nm and below. In addition, robust layout patterns that exhibit higher yield during normal manufacturing variations can be maximized.
The Si2 OPAL Working Group will manage the Intel contribution and entertain proposals on how to use, improve, document and distribute the new technology which can be used either stand alone or integrated on top of the OpenAccess database. OPAL’s geometric expressions can accurately and concisely describe user-specific layout constraints of any complexity.
Join a team of industry experts that will present and discuss this exciting new capability, while you enjoy a lunch at DAC.
Advanced Registration Required. Lunch Included Si2 Members: $50 Nonmembers: $90 No cancellations after June 10. CLICK HERE TO REGISTER
Gyuszi Suto graduated from 1987 from the Technical University of Cluj-Napoca, Romania, with a degree in Computer Science and Engineering. He has been with Intel since 1993, where he has worked on several generations of design-rule models and synthesis tools spanning process nodes measured in microns down to (a few) nanometers.
Gyuszi holds four patents related to physical design. His passions include drawing, math, puzzles, programming (C++), and teaching. He is also the main organizer of Intel’s internal annual programming contest. His name is Hungarian, and pronounced similar to Juicy, as in Juicy Fruit.
Chief Technical Officer
Motivo Data Analytics
Dr. Luigi Capodieci has worked on lithographic imaging, patterning and process simulations for more than 20 years, with applications to optical proximity correction, phase shift masks, resolution enhancement technology and design/process co-optimization. At Advanced Micro Devices, he pioneered the field of Design For Manufacturability (DFM), integrating physical design CAD flows with rigorous layout printability process modeling and novel verification algorithms. He was director of DFM/CAD at GLOBALFOUNDRIES from 2009 – 20015, managing DFM R&D from 45 and 32/28nm, down to the next generations of 22 and 14nm technology nodes. In 2015, Dr. Capodieci was elected Engineering Fellow, responsible for Design Enablement and DFM technology strategy for all the advanced nodes. In 2016 he founded KnotPrime, a data analytics startup company working in anomaly detection and applied algorithmic intelligence. He is currently CTO of Motivo Data Analytics.
Dr. Capodieci holds a Doctor degree in Electronic Engineering and Computer Science from the University of Bologna, Italy and a Ph.D. in Electrical Engineering, from the University of Wisconsin-Madison, where he worked at the Center for Nanotechnology (CNTech, formerly Center for X-Ray Lithography). He has authored and co-authored more than 70 journal and conference technical publications and is the principal inventor or co-inventor in 40 U.S. Patents. He is also an active member of the IEEE and ACM technical organizations and serves as the Chair of the DFM Conference at the SPIE Advanced Lithography Symposium. In 2015 he was elected to the rank of SPIE Fellow.
Maarten Berkens has been working on physical design optimization, yield enhancement and design rule modeling for more than 20 years. At Philips Semiconductors, Maarten was a team leader for non‐volatile memory development. In 1997 Maarten joined Sagantec as CTO, where he architected and led the team that developed the world’s first commercial hierarchical layout compaction tool that enabled early implementation of CPUs and custom ICs in new process technologies.
In 2004, he joined Takumi Technology as CTO, and led a team that developed DFM tools and flows, pioneering the integration of manufacturing modeling with physical design optimization and delivering solutions for hotspot reduction, yield enhancement and mask inspection and optimization. In 2012 Maarten co‐founded Sage Design Automation, where he currently serves at CTO. At Sage-DA, Maarten is the chief architect of iDRM: an integrated design rule management platform and DRC automation solution. Maarten holds an MSc. EE degree (honors) from the Eindhoven University of Technology, and is the principal inventor or co‐inventor in numerous patents in the fields of circuit design, design automation and design for manufacturing.
Who Should Attend
Si2 and potential Si2 members who have an interest in finding and marking specific 2D patterns in mask layout using the geometric expressions of a high-level, declarative language.
What You Will Learn
Learn by example using OPAL pattern analysis to find and annotate several well know yield detractors in sub-20nm layouts.
Join Us at DAC 2017 as Si2 Launches Special Interest Groups
For our OpenAccess and Open PDK Programs
Si2 is organizing Special Interest Groups to guide research and development activities its expanding OpenAccess and Open PDK programs. SIGs set up under the anti-trust protection of Si2 allow members to solve design problems with other companies in the industry, sharing hundreds of years of knowledge of designers to address common issues.
Si2, as a research and development joint venture, provides an opportunity to collaborate with like-minded companies to identify, document and even solve problems in the electronics/photonics design fields. The SIG can create industry surveys to find and prioritize the issues and work with other industry groups to develop roadmaps. Members can jointly write white papers and present at conferences. Using the Si2 infrastructure, a SIG can spawn projects including prototyping implementations, developing standards and creating training and documentation.
Interested in learning more?
CLICK HERE to register and bring your ideas for collaborative activities to DAC 2017.
Don’t Miss Another Si2 PDK-focused DAC Event:
Customizing PDKs for Design Specific Requirements
Can your power model deliver power data at ANY temperature-voltage combination, not just the pre-characterized values? Ours can!
Can your power model be used with BOTH gate level AND system level tools? Ours can!
Can your power model effortlessly switch between implementation technologies, such as planar CMOS and FDSOI? Ours can!
How many different PVT corners must your power models be pre-characterized for? None for us. And we can generate power models, on demand, for any PVT corner, not just the corners chosen in advance!
Energy and power concerns continue to grow and become more challenging in all design phases. Increasing attention is being paid to modeling techniques for system- and software-level power management. Today, multiple modeling standards are being developing and evolving to address these challenges, covering the full range from low-level hardware to high-level software. Each standard is evolving to address particular problems, but the modeling space is sufficiently large that different capabilities are needed to cover highly varied applications and methodologies.
Due to the wide range of design and application scenarios, one modeling technology does not fill all power modeling needs. Software-level power modeling, representing a system’s power characteristics, forms a programmer’s view of power behavior. In this approach, all major hardware functions and how to control their power characteristics are abstracted. Functions can be put into low-power states as often as possible by real-time power management software. System-level power modeling tends to focus on the hardware description of the system and its power behavior.
The system may be described in System C or RTL, or even in spreadsheets during the earliest design phases. It often focuses on meeting localized thermal constraints. Both of these modeling approaches differ from conventional gate-level modeling in which process-voltage-temperature (PVT) specific power models are built only for primitive logic cells, such as Nand and Nor gates, multiplexors, and flip-flops.
This tutorial will present the latest state of the IEEE 1801, 2415, and 2416 power standards, and show why multiple standards are required to cover the broad design and operational space. Speakers will explain the features of these three standards and how they enable new capabilities and power management methods. Early users of the standards and underlying technologies will describe how the new modeling capabilities impacted their design processes and end products.
• Developers of the 1801 standard for Power Intent will describe recent extensions for Power State modeling. These enhancements enable the description of the power state space for IP Blocks and hardware systems.
• Developers of the 2415 standard, currently in development, will describe their work on a power hardware abstraction and layer based upon the Linux Device Tree. Prototype usage of this hardware abstraction will also be presented.
• Developers of the 2416 standard for Power Data modeling, also currently in development, will describe their power contributor approach for PVT independent power modeling.
They will also describe how such models can be used with conventional gate- level tools and system-level modeling, including detailed electro-thermal analyses. This tutorial is intended for engineers concerned about power (software, EDA, IP, and SoC developers) who want to understand advanced power modeling, and which standard is best applied to different applications.
Nagu Dhanwada, IBM Systems Group, Poughkeepsie, NY
Jerry Frenkil, Silicon Integration Initiative, Inc., Austin, TX
Davorin Mista, Aggios, Inc., Irvine, CA
Amit Srivastava, Synopsys, Inc., Mountain View, CA
ID-Xplore: OpenAccess-based software for constraint-driven
analog design and migration at Functional Level
Founder and CEO
With the emerging era of the Internet-of-Things, analog designers will face huge challenges to boost their productivity. The productivity gap related to Moore’s Law will be further broadened due to the heavy computations in simulators and the impact on their design time and cost.
Intento presents Si2 OpenAccess-based constraint-driven design and migration methodology. It is based on graph theory, offering huge acceleration of both tasks at the functional level. A design graph is automatically created from OpenAccess constraint/schematic views. Each graph is deterministic, correct-by-construction and technology-independent. The key idea is to replace simultaneous resolution of linearized nodal equations inside SPICE-like simulators, by structured resolution of nonlinear DC transistor equations. Consequently, the high-order Jacobian matrices shrinks to only one element per transistor and matrix inversion is eliminated.
What You’ll Learn
ID-Xplore features and benefits
OpenAccess-based graph technology
The concept of incremental design
Accelerating design tasks
Migrating an existing Analog IP in just few clicks
About the Speaker
Dr. Ramy Iskander is the founder and CEO of Intento Design, bringing to the company more than 20 years of industrial and academic experiences in computer-aided design. Before founding Intento, Dr. Iskander served as an associate professor at the University Pierre and Marie Curie, and has published more than 80+ scientific articles in the field of analog design automation. From 2012 to 2016, Dr. Iskander served as the scientific coordinator of the European FP7 project AUTOMICS, which is dedicated to circuit design, modeling and implementation of novel design methodologies for smart power ICs in the automotive industry.
Web Based OpenAccess Viewer Using GO
What You’ll Learn
How to bind the OpenAccess API to any other programming language using SWIG.
How concurrency can help to efficiently create images from OpenAccess data.
About the Speaker
Larg H. Weiland received the Dr.-Ing. (Ph. D.) degree in computer science from the Karlsruhe Institute of Technology (KIT), Germany in 1998. In 1998 he joined PDF Solutions Inc. in San Jose, Calif. As a fellow he is responsible to provide technical direction and guidance for design automation product development. This includes creating design architectures and efficient workflow automation systems for design of experiment (DOE) composition for semiconductor yield enhancement, process optimization and process ramps as well as automated test structure design solutions for state of the art semiconductor technology nodes like 7mn and below. Dr. Weiland has published more than 40 conference and journal papers and holds various patents. He is member of the IEEE and the Electron Devices Society. He has served as conference chair and in the technical committee of several semiconductor manufacturing related conferences. He was the Technical Chair of the 2012 International Conference on Microelectronic Test Structures (ICMTS) and General Chair of the ICMTS in 2015.
Finfet/multipatterning process analog design automation and Static Timing Analysis
Analog Rails is a fully automatic and drc/lvs correct by construction ™ fully synchronized analog/mixed-signal IC design platform built natively on Si2 OpenAccess. Our comprehensive environment synchronizes schematic, layout, simulation, optimization, sensitivity, automatic placers and routers, RCx, IR drop and EM, allowing circuit designers to reduce design time by over 10x.
Digital Rails is due to release in 2017-q4.
What You’ll Learn/Benefits
Over 10x labor efficiency. A $200K engineer will be worth $2M+
Quicker time to market
More time to do trade-offs
More time to verify. Save mask sets, test/troubleshooting time
In control of their own layouts, which will improve the quality.
Ability to design bottom=>top=>bottom=>top. Why limit yourself?
Create IP on different foundries (2nd source)
Protect IP. No need to outsource.
No EDA empire needed.
About the Speaker
Cliff Wiener is the founder of Get2spec, Inc. (DBA Analog Rails). He was a former analog circuit designer and was in charge of analog design methodologies at National Semiconductor and Motorola Semiconductor before starting Get2spec in 2004.
OpenAccess Script brings unmatched power and flexibility to EDA engineers. It opens the door to the OA database by allowing engineers to easily write OA scripts using the industry’s most popular languages: Perl, Python, Ruby and Tcl. Join us for two oaScript success stories, and an introduction to our new integrated learning system for OpenAccess and oaScript.
Experience how OpenAccess and oaScript
Solve Your Specific Design Challenges
Registered attendees are eligible to receive a demonstration copy of the tool.
In many traditional design flows, high-performance robust EDA capabilities are limited to formal EDA tools. Design Automation (DA) engineers build additional project-specific capabilities either by using an EDA tool’s proprietary scripting API or by creating a standalone lightweight script that relies upon translation of design data into other formats. This results in extra runtime overhead, additional possible points of failure, and a burden of working with lossy design data formats.
With the advent of oaScript, DA engineers can quickly write scripts that directly read and write OpenAccess (data using one of their favorite scripting languages – Perl, Python, Ruby, or Tcl. Also, a new OA extension — “oaxPop” (OA eXtension Polygon Operators) — provides high-speed layer manipulation and boolean operations directly within an oaScript. The combination of oaScript with oaxPop enables a DA engineer to write high-performance robust EDA capabilities without the overhead of using a formal EDA tool.
What You’ll Learn
How oaScript and oaxPop combine to create real-life applications that are used in a production design flow.
About the Speaker
James Masters graduated from the University of Phoenix with a Bachelor of Science in Information Technology with an emphasis on computer programming. He has worked at Intel Corporation for more than 20 years in various full-custom design implementation roles.
James is currently managing a team focused on improving custom layout productivity for Intel’s advanced process technologies. He is an advocate of open standards that help streamline the design flow and maximize productivity and reuse.
A Scripting Environment for Efficient Design Creation
President and Owner
Using scripts in the design flow is a common task. But the efficient design of scripts can be a challenge. Useful tools and a sophisticated development environment can boost scripting productivity. In this presentation, we will discuss how to get started with oaScript faster and be more productive.
What You’ll Learn
Getting started with oaScript
Scripting in Python, Ruby and TCL
Mixing oaScript with other scripting extension modules
Debugging scripts and designs
About the Speaker
Jürgen Thies founded the LayoutEditor project in 2004 as open-source software for editing IC and MEMS designs. In 2009 LayoutEditor became a commercial but still inexpensive application often use for high-end applications beyond the mainstream. Jürgen is owner and president of Juspertor GmbH, the company behind LayoutEditor software.
Interactive, On-Demand Training for the OpenAccess Standard and Scripting
Si2 and its partner, Semitracks, have developed an interactive, on-demand training site to help engineers learn about the OpenAccess standard and how to write simple scripts to harness the power of OA. The site is based on an industry-standard Learning Management System (Moodle). It provides unique user accounts and password for the engineer, the ability to systematically cover topics related to the OA standard and scripting, interactive course materials to “learn by doing” and quizzes to test the engineer’s knowledge and retention. Once complete, the user can print out a certificate of completion. The system is also a reference source for potential OpenAccess questions. Si2 will add content in the future to provide even more in-depth training on this important topic.
What You’ll Learn
An overview of the Learning Management System
How to log in and access materials
What materials are currently available in the system
How a course section works
How a quiz works
How to print a certificate of completion
About the Speaker
Chris Henderson received his B.S. in Physics from the New Mexico Institute of Mining and Technology and his M.S.E.E. from the University of New Mexico. Chris is the president and one of the founders of Semitracks Inc., a United States-based company that provides education and training to the semiconductor industry. From 1988 to 2004 he worked at Sandia National Laboratories, where he was a principal member of Technical Staff in the Failure Analysis Department and Microsystems Partnerships Department. His job responsibilities have included reliability, failure and yield analysis of components fabricated at Sandia’s Microelectronics Development Laboratory, research into the electrical behavior of defects, and consulting on microelectronics issues for the Department of Defense.