Unified Power Model
Reduce or eliminate blown system thermal and power budgets and schedules by significantly improving system design/power estimation cycle time and accuracy.
Chair: Nagu R. Dhanwada, IBM
Chip Package Co-Design
Reduce or eliminate inefficiencies in the codesign of SoCs and 3D and 2.5D design flows by improving, or creating as needed, standardized communication of electro-thermal-mechanical parameters between designers, suppliers, and their design toolsets.
Chair: Tom Whipple, Zuken, Inc.
Open Pattern Advanced Layout
Rapidly search an OpenAccess layout for yield-detracting patterns or particularly robust patterns with a specialized language for 2D pattern analysis targeted at advanced processes at 20nm and below.