- Can your power model deliver power data at ANY temperature-voltage combination, not just the pre-characterized values? Ours can!
- Can your power model be used with BOTH gate level AND system level tools? Ours can!
- Can your power model effortlessly switch between implementation technologies, such as planar CMOS and FDSOI? Ours can!
- How many different PVT corners must your power models be pre-characterized for? None for us. And we can generate power models, on demand, for any PVT corner, not just the corners chosen in advance!
Energy and power concerns continue to grow and become more challenging in all design phases. Increasing attention is being paid to modeling techniques for system- and software-level power management. Today, multiple modeling standards are being developing and evolving to address these challenges, covering the full range from low-level hardware to high-level software. Each standard is evolving to address particular problems, but the modeling space is sufficiently large that different capabilities are needed to cover highly varied applications and methodologies.
Due to the wide range of design and application scenarios, one modeling technology does not fill all power modeling needs. Software-level power modeling, representing a system’s power characteristics, forms a programmer’s view of power behavior. In this approach, all major hardware functions and how to control their power characteristics are abstracted. Functions can be put into low-power states as often as possible by real-time power management software. System-level power modeling tends to focus on the hardware description of the system and its power behavior.
The system may be described in System C or RTL, or even in spreadsheets during the earliest design phases. It often focuses on meeting localized thermal constraints. Both of these modeling approaches differ from conventional gate-level modeling in which process-voltage-temperature (PVT) specific power models are built only for primitive logic cells, such as Nand and Nor gates, multiplexors, and flip-flops.
This tutorial will present the latest state of the IEEE 1801, 2415, and 2416 power standards, and show why multiple standards are required to cover the broad design and operational space. Speakers will explain the features of these three standards and how they enable new capabilities and power management methods. Early users of the standards and underlying technologies will describe how the new modeling capabilities impacted their design processes and end products.
• Developers of the 1801 standard for Power Intent will describe recent extensions for Power State modeling. These enhancements enable the description of the power state space for IP Blocks and hardware systems.
• Developers of the 2415 standard, currently in development, will describe their work on a power hardware abstraction and layer based upon the Linux Device Tree. Prototype usage of this hardware abstraction will also be presented.
• Developers of the 2416 standard for Power Data modeling, also currently in development, will describe their power contributor approach for PVT independent power modeling.
They will also describe how such models can be used with conventional gate- level tools and system-level modeling, including detailed electro-thermal analyses. This tutorial is intended for engineers concerned about power (software, EDA, IP, and SoC developers) who want to understand advanced power modeling, and which standard is best applied to different applications.
Nagu Dhanwada, IBM Systems Group, Poughkeepsie, NY
Jerry Frenkil, Silicon Integration Initiative, Inc., Austin, TX
Davorin Mista, Aggios, Inc., Irvine, CA
Amit Srivastava, Synopsys, Inc., Mountain View, CA
Register at www.dac.com
(Monday) 3:30 pm - 5:00 pm