19jun11:00 am- 1:00 pmDAC Event: Introducing OPAL -- A High-Level Design Rule Modeling Language11:00 am - 1:00 pm CST Austin Convention Center--Room 7Event Organized By: Silicon Integration Initiative
Discover the Power Of OPAL,
A New High-Level Design Rule
Recently donated to Si2 by Intel, OPAL is a high-level, layout modeling language for 2D pattern analysis. It is an object-orientated, declarative language that accurately describes a wide variety of problematic patterns known as hotspots. These patterns exhibit poor image transfer during lithography at 20nm and below. In addition, robust layout patterns that exhibit higher yield during normal manufacturing variations can be maximized.
The Si2 OPAL Working Group will manage the Intel contribution and entertain proposals on how to use, improve, document and distribute the new technology which can be used either stand alone or integrated on top of the OpenAccess database. OPAL’s geometric expressions can accurately and concisely describe user-specific layout constraints of any complexity.
Join a team of industry experts that will present and discuss this exciting new capability, while you enjoy a lunch at DAC.
Advanced Registration Required.
CLICK HERE TO REGISTER
Technical Lead and Co-Author
of OPAL at Intel Corp.
Gyuszi Suto graduated from 1987 from the Technical University of Cluj-Napoca, Romania, with a degree in Computer Science and Engineering. He has been with Intel since 1993, where he has worked on several generations of design-rule models and synthesis tools spanning process nodes measured in microns down to (a few) nanometers. Gyuszi is the main architect and co-author of the boost::Polygon library on which oaxPop is based.
Gyuszi holds four patents related to physical design. His passions include drawing, math, puzzles, programming (C++), and teaching. He is also the main organizer of Intel’s internal annual programming contest. His name is Hungarian, and pronounced similar to Juicy, as in Juicy Fruit.
Principal Member of the Technical Staff
Advanced Micro Devices
Jason Cain works in the field of Design for Manufacturability (DFM) at Advanced Micro Devices (AMD) in Austin, Texas, where he is currently Principal Member of the Technical Staff. Since joining AMD in 2004, his career has spanned several fields including lithography, semiconductor metrology, advanced process control, factory automation, optical proximity correction and resolution enhancement techniques. In his current role, Dr. Cain is responsible for leading the DFM team to enable manufacturable test chip and product designs at leading edge technology nodes down to 7nm. Dr. Cain has published more than 40 technical papers and holds four United States patents. He received the B.S. degree in electrical engineering from Texas A&M University in 1999 and the M.S. and Ph.D. degrees from the University of California, Berkeley in 2002 and 2004, respectively.
Chief Technical Officer
Motivo Data Analytics
Dr. Luigi Capodieci has worked on lithographic imaging, patterning and process simulations for more than 20 years, with applications to optical proximity correction, phase shift masks, resolution enhancement technology and design/process co-optimization. At Advanced Micro Devices, he pioneered the field of Design For Manufacturability (DFM), integrating physical design CAD flows with rigorous layout printability process modeling and novel verification algorithms. He was director of DFM/CAD at GLOBALFOUNDRIES from 2009 – 20015, managing DFM R&D from 45 and 32/28nm, down to the next generations of 22 and 14nm technology nodes. In 2015, Dr. Capodieci was elected Engineering Fellow, responsible for Design Enablement and DFM technology strategy for all the advanced nodes. In 2016 he founded KnotPrime, a data analytics startup company working in anomaly detection and applied algorithmic intelligence. He is currently CTO of Motivo Data Analytics.
Dr. Capodieci holds a Doctor degree in Electronic Engineering and Computer Science from the University of Bologna, Italy and a Ph.D. in Electrical Engineering, from the University of Wisconsin-Madison, where he worked at the Center for Nanotechnology (CNTech, formerly Center for X-Ray Lithography). He has authored and co-authored more than 70 journal and conference technical publications and is the principal inventor or co-inventor in 40 U.S. Patents. He is also an active member of the IEEE and ACM technical organizations and serves as the Chair of the DFM Conference at the SPIE Advanced Lithography Symposium. In 2015 he was elected to the rank of SPIE Fellow.
Chief Technical Officer
Sage Design Automation
Maarten Berkens has been working on physical design optimization, yield enhancement and design rule modeling for more than 20 years. At Philips Semiconductors, Maarten was a team leader for non-volatile memory development. In 1997 Maarten joined Sagantec as CTO, where he architected and led the team that developed the world’s first commercial hierarchical layout compaction tool that enabled early implementation of CPUs and custom ICs in new process technologies.
In 2004, he joined Takumi Technology as CTO, and led a team that developed DFM tools and flows, pioneering the integration of manufacturing modeling with physical design optimization and delivering solutions for hotspot reduction, yield enhancement and mask inspection and optimization. In 2012, Maarten co-founded Sage Design Automation, where he currently serves at CTO. At Sage, Maarten is the chief architect of iDRM: an integrated design rule management platform and DRC automation solution. Maarten holds an MSc. EE degree (honors) from the Eindhoven University of Technology, and is the principal inventor or co-inventor in numerous patents in the fields of circuit design, design automation and design for manufacturing.
Who Should Attend
Si2 and potential Si2 members who have an interest in finding and marking specific 2D patterns in mask layout using the geometric expressions of a high-level, declarative language.
What You Will Learn
Learn by example using OPAL pattern analysis to find and annotate several well know yield detractors in sub-20nm layouts.
(Monday) 11:00 am - 1:00 pm CST
Austin Convention Center--Room 7
500 E Cesar Chavez St, Austin, TX 78701
Silicon Integration Initiative9111 Jollyville Road, Austin TX 78759