In just over 10 years, process nodes will shrink from 100nm in 2005 to 10nm in 2017. An upsurge in the complexity of advanced DRC decks makes it almost impossible to code rule decks using basic Pass/Fail DRC rules. The exponential increase in the design rule count and the number of operations required by complex DRC rules has made physical verification run times longer and increases debug times. A panel of four industry experts representing design, implementation, verification and manufacturing will describe their own personal experiences and best practices for developing DRC decks for 10nm processes.
Moderator: Jake Buurma, Senior Fellow, Si2
Mike Willet, Texas Instruments
Dave Doman, Director of CMOS Library Design, GLOBALFOUNDRIES
Raul Camposano, CEO, Sage Design Automation
Brian Veraa, Chip Architect and Integrator, Qualcomm