IEEE Approves New Power Modeling Standard. 2416-2019 Built on Si2 Unified Power Model

AUSTIN, Texas–Silicon Integration Initiative has announced that its Unified Power Model, developed with major contributions from IBM and GLOBALFOUNDRIES, has been approved as IEEE 2416-2019, a new Standard for Power Modeling to Enable System Level Analysis, which complements UPF/IEEE 1801-2018 Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems.

Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

UPM/IEEE 2416-2019 provides a rich set of power modeling semantics enabling system designers to model entire systems with great flexibility. It supports power modeling from abstract design description all the way to gate level implementation providing data consistency from earliest architectural explorations to final power verification.

“We view UPM/IEEE 2416 as a major step forward for low power design,” commented Dr. Nagu Dhanwada of IBM, chair of the IEEE 2416 and the Si2 UPM Working Groups.

“The foundation of the UPM/IEEE 2416-2019 standard originated in IBM and has been successfully used in power sign-off of several generations and families of IBM microprocessors. Concepts like multi-level, state-based modeling and efficient, expressive semantics in UPM/IEEE 2416-2019 support constructing accurate and standardized power models for IP blocks. This enables SoC designs to be energy efficient from the ground up, a key reason companies will use 2416-2019 to upgrade modeling, analysis and sign-off flows,” stated Dr. Dhanwada.

Si2 UPM is a product of the Si2 OpenStandards Coalition, an R&D incubator which rapidly seeds and prototypes potential new EDA software tool interoperability standards. “The target of this development and subsequent standardization was an efficient and flexible mechanism for the specification and interchange of consistent power models throughout a project’s lifetime, from system design to manufacturing, especially for IP blocks and chiplets,” said Jerry Frenkil, Si2 director of OpenStandards. “This work led to significant advances in power modeling, including contributor and multi-level modeling, both of which are included in the 2416-2019 standard.”

A prototype power tool, upmPowerCalc, was built to prove the new concepts from end-to-end, both accelerating the delivery of a ready-to-implement standard and providing OpenStandards members with tools to aid in their own implementation.” The Si2 work was supported by the UPM Working Group consisting of ANSYS, IBM, Intel, Cadence, Entasys, and Thrace Systems.

Power contributors are Process, Voltage, and Temperature independent proxies for power. This PVT independence enables the late binding of PVT conditions at simulation run time, enabling power analysis at various PVT corners without requiring new libraries. Multi-level models provide multiple model views, or interfaces, to access the same power data. With multi-level construction, a single model provides consistent data for both system-level abstract simulations and bit-level simulations with RTL or gates.

“These advancements, along with UPM’s semantic expressiveness, deliver multiple benefits for design organizations” Frenkil explained. “System architects and SoC designers can model entire systems at a variety of PVT points with great flexibility. Power can be modeled in UPM using scalars, tables, expressions, and contributors, as well as expressions referencing contributors.”

UPM’s expressiveness also provides major benefits for IP developers. The use of power contributors leads to significant productivity gains since far fewer models and libraries are needed with UPM’s PVT independence. In addition, the models are abstract black boxes – functionality cannot be reverse-engineered from the power models.

Model interoperability and consistency with UPF/IEEE 1801 were identified early on as key goals in support of increasing emphasis on system level design. “IEEE 2416 provides a standardized interoperable system-level power model that is an essential piece of the foundation of an emerging industry-scale chiplet ecosystem” commented Ramune Nagisetty, senior principal engineer and director of Process and Product Integration at Intel Corporation.

“Energy-aware, system-level design can be a challenging task,” added John Biggs, chair of the IEEE P1801 Working Group, and distinguished engineer and co-founder of Arm. “With this new standard, designers will be better enabled by having access to semiconductor IP delivered with both IEEE 1801 power state models and IEEE 2416 power data models.”

For design automation groups, UPM provides an industry-standard format for both internal and external IP. This common format saves resources and time as there is no need to support or translate external proprietary formats. UPM also reduces reliance on internal proprietary formats, a long-standing design obsolescence trap.

An EDA startup, Thrace Systems, is planning to add IEEE 2416 support to its products. “UPM/IEEE 2416 is an important new standard. Its rich modeling semantics provide our power analysis platform with the solid infrastructure needed for comprehensive system level analysis,” commented David Ratchkov, Thrace Systems founder and CEO.

The P2416 Working Group was led by IBM, Si2, and Cadence, with active support from Intel and Arm.

For more information contact Jerry Frenkil at jfrenkil@si2.org.

IBM, GLOBALFOUNDRIES Enhance Si2 Unified Power Model Standard

Si2 has announced  that IBM and GLOBALFOUNDRIES have contributed patented technology to support the Si2 Unified Power Model standard, the industry’s first significant power model enhancement in many years.

Early stage estimation of System on Chip power consumption is fundamental to ensuring new SoC designs meet or exceed power specifications when fabricated. For a credible estimate, the power models must comprehend the target implementation technology and circuitry, along with voltage and temperature conditions. At the same time, power estimation results are needed quickly in to perform rapid “what if” scenarios.

UPM’s multi-level power modeling capability provides the necessary level of modeling detail required at various stages of design. Abstract high-level equations to gate-level characterization tables can be accommodated through the same, standard interface. Beyond this, the UPM interface, upon acceptance and approval by the IEEE’s P2416 working group, will be a direct plug-in to the widely-used IEEE 1801 stub created for power models.

Simplified Power Modeling

The IBM and GF contributions enhance UPM by providing a new and unique approach to power modeling. Rather than storing pre-characterized, process-voltage-temperature specific data, UPM models store power proxies that represent different contributors to overall power consumption, such as sub-threshold leakage, gate leakage, and dynamic power. Appropriately entitled “power contributors,” this approach vastly simplifies and reduces the power modeling effort, and allows the power model to be voltage and temperature independent, enabling a single power model to be used at a multitude of voltages and temperatures.

SoC designers using UPM with contributor-based modeling will ultimately be equipped with thermally-aware, system-level power estimation. In addition, the late-binding of specific PVT conditions at simulation run-time will provide accurate, early estimates of leakage power, which increases exponentially with increasing temperature. The donated technology covers key aspects of contributor-based power modeling including model abstraction, generation, compression and evaluation.

Contributor-based modeling will be fully integrated into UPM, which forms the basis for P2416, the planned IEEE standard for developing and maintaining interoperable, IC design power models.  P2416 is scheduled for balloting in early 2019.

Industry Contributions

Jerry Frenkil, director of Si2 OpenStandards, said the IBM and GF contributions bolster UPM and provide P2416 with proven and ready-to-use modeling methods.  “These power proxies enable voltage and temperature-independent modeling which greatly reduce the model generation and support effort,” Frenkil explained. “They also enable late binding of voltage and temperature conditions at simulation run-time, a major benefit for both IP developers and SoC designers.”

“IBM is pleased to donate this advanced modeling technology to Si2’s UPM development to facilitate interchange of IP power data,” said Dr. Leon Stok, vice president of EDA at IBM.  “We have used contributor modeling internally on several generations of IBM micro-processors to great effect. We look forward to seeing UPM contributor models being provided by IP block developers so that entire systems, consisting of both internal and external IP, can be modeled efficiently using a common modeling standard.  Additionally, the combination of power contributors and multi-level modeling structures promises major cost and resource improvements in creating and supporting IP power models.”

“UPM directly addresses a major industry need—accurate and efficient system-level power models,” said Richard Trihy, senior director of design enablement at GF.  “Since IP providers need only produce a single model for a multitude of PVT points, these models enable significant productivity gains in model generation. Our clients will also get a good early estimate of their systems’ total power, including leakage, which can operate at high temperatures.”

Ready for P2416 Balloting

“These contributions from IBM and GF come at a fortuitous time,” said Dr. Nagu Dhanwada of IBM, chair of the IEEE P2416 Working Group and the Si2 UPM development project.  “The P2416 Working Group is rapidly gathering momentum towards IEEE standardization.  We anticipate going to ballot early next year.”

For more information about this project, contact Jerry Frenkil at jfrenkil@si2.org.  For information about the Low Power Working Group and other OpenStandards programs, visit http://www.si2.org/openstandards/.