DAC 2016 Panel Discussion on DFM/DRC: The Insanity of DRC Rules and DFM and 10nm and Below

In just over 10 years, process nodes will have shrunk from 100nm in 2005 to 10nm in 2017. An upsurge in the complexity of advanced DRC decks makes it almost impossible to code rule decks using basic Pass/Fail DRC rules. The exponential increase in the design rule count and the number of operations required by complex DRC rules has made physical verification run times longer and increases debug times. A panel of four industry experts representing design, implementation, verification and manufacturing will describe their own personal experiences and best practices for developing DRC decks for 10nm processes.

 

Panelists
Moderator: Jake Buurma, Senior Fellow, Si2
Mike Willet, Texas Instruments
Dave Doman, Director of CMOS Library Design, GLOBALFOUNDRIES
Raul Camposano, CEO, Sage Design Automation
Brian Veraa, Chip Architect and Integrator, Qualcomm

Presentation by: Raul Camposano, CEO, Sage Design Automation 

Presentation by: Mike Willet, Texas Instruments

Presentation by: Dave Doman, Director of CMOS Library Design, GLOBALFOUNDRIES 

 

 

 

 

 

Chip/Package/Board Co-Design and Co-Analysis: Moving from Spreadsheets to EDA

DAC 2016:

Description

SoC development has become more than just silicon design. Today, successful SoC design requires consideration of the electrical, thermal, and mechanical interactions of the chip, the package and the board. This is especially true for silicon-in-package designs and 3D designs such as Hybrid Memory Cubes and High Bandwidth Memories. Co-design of the silicon and the package has become essential. This panel will present and discuss different challenges with and approaches to co-design and co-analysis.

What you will learn

  • Recent developments in 3D and co-design

  • Challenges and solutions in automating co-design and co-analysis

  • Applications most in need of co-design and co-analysis

Panelists

  • Moderator, Jerry Frenkil, Director of OpenStandards, Si2

  • Humair Mandavia, Chief Strategy Officer, Zuken

  • Brandon Wang, Group Director, Cadence Design Systems

  • Teresa McLaurin, ARM

 

Si2 contributes advanced IC power modeling technology to IEEE.

Si2 Contributes Advanced IC Power
Modeling Technology to IEEE

Technology will improve SoC design for power efficiency

AUSTIN, Texas–Silicon Integration Initiative, Inc. (Si2), a leading integrated circuit research and development joint venture, has contributed new power modeling technology to the IEEE P2416 System Level Power Model Working Group. The transfer is aimed at creating a standardized means for modeling systems-on-chip (SoC) designed for lower power consumption.

Jerry Frenkil, Si2 director of OpenStandards, said that the Si2 Low Power Working Group developed the new technology to fill several holes in the flow for estimating and controlling SoC power consumption. “This new modeling technology provides accurate and efficient, early estimation of both static and dynamic power, including critical temperature dependencies, using a consistent model throughout the design flow. There’s currently no standard way to represent power data for use at the system level, especially across a range of process, voltage and temperature points in a single model.”

IEEE P2416 is an essential component of IEEE’s coordinated effort to improve system-level design. This effort also includes the IEEE 1801 standard, which expresses design intent.  Its latest update, IEEE 1801-2015, includes support for power-state modeling.  “P2416 provides power data representations to complement 1801 power-state modeling.  Together, 1801 and 2416 will form a complete power model for hardware IP at any level of abstraction” Frenkil added.

Organizations that contributed to the model development are:  ANSYS, Cadence, Intel, IBM, Entasys, and North Carolina State University.

Nagu Dhanwada, senior technical staff member at IBM, chairs both the IEEE P2416 and Si2 Power Modeling Working Groups. According to Dhanwada, “This is a major contribution to the P2416 effort. As the first technology contribution to the P2416 Working Group, it’s expected to form a solid foundation for the resulting standard.”

“This new modeling technology is the first significant advance in power modeling in quite a long time” said Paul Traynar, technical fellow at ANSYS and a contributor to the Si2 effort.  “It will enable SoC designers to get consistent power estimates across design abstractions and especially early in the system design process.”

Julien Sebot, CPU architect at Intel and a member of the IEEE P2416 Working Group, added, “The Si2 contribution addresses the top priorities identified by the P2416 Working Group. The ability to create accurate, early estimates and to reuse and refine those estimates during the design process is essential in creating energy efficient systems-on-chip.  Si2’s contribution is a major step toward addressing that need.”

The IEEE-P2416 Working Group has already started reviewing the Si2 contribution.  In parallel, Si2 will further develop, for its members, the technology with expanded model semantics, proof-of-concept demonstrations, and reference design implementations.

This model and its use will be described as part of a DAC 2017 tutorial, “How Power Modeling Standards Power Your Designs,” Monday, June 19, 3:30-5:00 p.m., Room 18AB, Austin Convention Center.

For more information about this project, contact Jerry Frenkil at [email protected].  For information about the Si2 Low Power Working Group and other OpenStandards programs, visit https://si2.org/openstandards/.

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.  All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. Si2’s international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.

 

Silicon Photonics Membership Agreement

The Silicon Photonics Coalition requires agreement to the following documents:

SP TAB Membership Agreement

SP TAB Project Operating Rules

OpenPDK Membership Agreement

OpenPDK Membership requires the following documents:

 

OPEN PDK COALITION MEMBERSHIP AGREEMENT  – form and signature required.
OpenPDK Coalition Operating Rules  –  Review and understanding required

 

Si2 Low Power Membership Agreement

The Si2 LOW POWER COALITION  requires the following membership agreements:

First:  LOW POWER COALITION MEMBERSHIP AGREEMENT 01/2008

Second:  Low Power Coalition Operating Rules

CHIP – PACKAGE CO – DESIGN ( OPEN3D ) Membership Agreement

Membership in the Si2 Chip-Package Co-Design (aka (Open3D))  requires agreement to the following documents.

First:   CHIP-PACKAGE CO-DESIGN (OPEN3D)MEMBERSHIP AGREEMENT

Second:  DTMC__DFMC__Operating_Policy-1.pdf:  Attachment C- Project IP Policy

 

OpenDFM Membership Agreements

OpenDFM Membership Required Documennts

First:  SILICON INTEGRATION INITIATIVE, INC. DESIGN TO MANUFACTURING COALITION MEMBERSHIP AGREEMENT 01-20-2016

See below:

Second:  Design to Manufacturing Coalition Operating Policy 1.07.2007 (01-20-2016)

See below:

Si2 Antitrust Guidelines

The Si2 Antitrust Guidelines are a fundamental part of our operation process. All members must agree to abide by these guidelines. This document is generally built into or referenced by each membership agreement or procedures document.