New Si2 Working Group to Develop Unified Power Model for System-Level IC Design

AUSTIN—Silicon Integration Initiative, Inc. (Si2), a research and development joint venture focused on integrated circuit design tool interoperability standards, has launched a System Level Power working group to create the Si2 Unified Power Model (UPM), a standard which will strengthen power management in system-level IC design.

Jerry Frenkil, director of the OpenStandards Coalition, which incubates new Si2 standards, said development of the Si2 UPM is part of the industry’s ongoing effort to improve energy and power efficiency throughout the system-on-a-chip development flow, with a focus on system design.

“Energy efficiency is a growing and costly constraint in integrated circuit design,” Frenkil explained.  “There’s currently no standard, single model to represent power data at the system level across a range of process, voltage, and temperature (PVT) points.  Different, often inconsistent models are currently used in each of the three major stages of IC design:  system design, register transfer level (RTL) design, and implementation.  None of those models currently support voltage or temperature dependencies.  The Si2 UPM addresses those issues.”

When completed, the Si2 UPM will enable faster turnaround time for system-level power and thermal analyses, as well as reduce resources and costs incurred in power model generation, Frenkil said.  The approved specification, including the capability to supply power data to IEEE 1801/UPF power state models, will be contributed to the IEEE P2416 Working Group for ongoing maintenance and industry-wide standardization. IEEE P2416 supports the ability to develop accurate, efficient and interoperable power models for complex, integrated circuit designs.

Si2 members participating in the working group are ANSYS (NASDAQ: ANNS), Cadence Design Systems (NASDAQ: CDNS), IBM (NYSE: IBM), Intel (NASDAQ: INTC) and Entasys.

The Si2 UPM will benefit the three major constituencies to the IC design ecosystem:

  • For IP providers:
    • A system-level power data model companion for the IEEE 1801 (UPF) power state model
    • reduced time and resources for model and library generation and support.
  • For system and SoC architects
    • true system-level modeling that eliminates the need for gate-level netlists.
    • faster turn-around time for system-level power and thermal analyses
    • model consistency across abstractions
  • For EDA providers
    • New, non-cannibalistic product and solution opportunities

For information about the new Si2 UPM working group or other Si2 OpenStandards projects, contact Jerry Frenkil, jfrenkil@si2.org.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust law.

Si2 Launches Effort to Improve IC Ecosystem

Si2 Launches Effort to Improve IC Design Ecosystem

New Special Interest Group Will Present Recommendations at DAC 2018

Si2 is seeking industry input on an international effort to identify and address ways to streamline and improve the IC design ecosystem. The finished product will be a DAC 2018 white paper whose contents will present an industry consensus on specific ways the industry can manage the rising costs of more complex designs and smaller geometries.

Ted Paone, Si2 interoperability standards architect, said the first step in the process was the formation of the Si2 Design Ecosystem Special Interest Group (SIG), which will write and distribute an industry-wide survey identifying areas of concern. The survey will launch in March 2018. Intel, Cadence Design Systems, Micron, Samsung, IBM and PDF Solutions are charter members of the SIG, which will investigate the impact of current issues in design and the expectations of future design requirements including performance and interoperability improvements to design data bases and scripting languages.

IC designers and engineers can submit survey questions for consideration at https://www.surveymonkey.com/r/9NSZCLC.

“We’re asking for the industry to help identify their specific design concerns so we can incorporate them into our survey,” he explained. “These are the people whose day-to-day activities are complicated by the need to create successful silicon while dealing with more and more complex processes, larger designs, new security and traceability issues, and emerging technologies such as chiplets, photonic elements and three-dimensional packaging.”

For information about the Si2 Design Ecosystem SIG, contact Paone, tedp@si2.org.  Information about joining the SIG is available at www.si2.org.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust law.

Tom Whipple Elected Co-Chair of Si2 OpenStandards Technology Steering Group

Tom Whipple, solutions architect at Zuken, has been elected co-chair of the Si2 OpenStandards Technology Steering Group. He joins co-chair Jerry Frenkil, director of OpenStandards, in this new leadership role.  Paul Stabler of IBM was elected secretary.

The Si2 OpenStandards membership offers the option for companies collaborate in one or all of a variety of  topical working groups that develop and approve standards for the global semiconductor industry. OpenStandards targets potential standards earlier, streamlines a path for more timely industry approval, and strengthens  inter-project collaboration. The TSG is responsible for coordinating OS technology roadmaps, and recommending formation of OS collaborating groups and monitoring their activities.

At Zuken, Tom is responsible for defining, promoting and supporting chip-package-board co-design solutions using Zuken CR-8000 design tools.

DAC 2016 Panel Discussion on DFM/DRC: The Insanity of DRC Rules and DFM and 10nm and Below

In just over 10 years, process nodes will have shrunk from 100nm in 2005 to 10nm in 2017. An upsurge in the complexity of advanced DRC decks makes it almost impossible to code rule decks using basic Pass/Fail DRC rules. The exponential increase in the design rule count and the number of operations required by complex DRC rules has made physical verification run times longer and increases debug times. A panel of four industry experts representing design, implementation, verification and manufacturing will describe their own personal experiences and best practices for developing DRC decks for 10nm processes.

 

Panelists
Moderator: Jake Buurma, Senior Fellow, Si2
Mike Willet, Texas Instruments
Dave Doman, Director of CMOS Library Design, GLOBALFOUNDRIES
Raul Camposano, CEO, Sage Design Automation
Brian Veraa, Chip Architect and Integrator, Qualcomm

Presentation by: Raul Camposano, CEO, Sage Design Automation dac_panel_dr-rc

Presentation by: Mike Willet, Texas Instruments si2_panel_insane_drc_10nm_willett-1

Presentation by: Dave Doman, Director of CMOS Library Design, GLOBALFOUNDRIES dac_slides_final-1

 

 

 

 

 

Chip/Package/Board Co-Design and Co-Analysis: Moving from Spreadsheets to EDA

DAC 2016:

Description

SoC development has become more than just silicon design. Today, successful SoC design requires consideration of the electrical, thermal, and mechanical interactions of the chip, the package and the board. This is especially true for silicon-in-package designs and 3D designs such as Hybrid Memory Cubes and High Bandwidth Memories. Co-design of the silicon and the package has become essential. This panel will present and discuss different challenges with and approaches to co-design and co-analysis.

What you will learn

  • Recent developments in 3D and co-design

  • Challenges and solutions in automating co-design and co-analysis

  • Applications most in need of co-design and co-analysis

Panelists

  • Moderator, Jerry Frenkil, Director of OpenStandards, Si2

  • Humair Mandavia, Chief Strategy Officer, Zuken

  • Brandon Wang, Group Director, Cadence Design Systems

  • Teresa McLaurin, ARM

 

Si2 contributes advanced IC power modeling technology to IEEE.

Si2 Contributes Advanced IC Power
Modeling Technology to IEEE

Technology will improve SoC design for power efficiency

AUSTIN, Texas–Silicon Integration Initiative, Inc. (Si2), a leading integrated circuit research and development joint venture, has contributed new power modeling technology to the IEEE P2416 System Level Power Model Working Group. The transfer is aimed at creating a standardized means for modeling systems-on-chip (SoC) designed for lower power consumption.

Jerry Frenkil, Si2 director of OpenStandards, said that the Si2 Low Power Working Group developed the new technology to fill several holes in the flow for estimating and controlling SoC power consumption. “This new modeling technology provides accurate and efficient, early estimation of both static and dynamic power, including critical temperature dependencies, using a consistent model throughout the design flow. There’s currently no standard way to represent power data for use at the system level, especially across a range of process, voltage and temperature points in a single model.”

IEEE P2416 is an essential component of IEEE’s coordinated effort to improve system-level design. This effort also includes the IEEE 1801 standard, which expresses design intent.  Its latest update, IEEE 1801-2015, includes support for power-state modeling.  “P2416 provides power data representations to complement 1801 power-state modeling.  Together, 1801 and 2416 will form a complete power model for hardware IP at any level of abstraction” Frenkil added.

Organizations that contributed to the model development are:  ANSYS, Cadence, Intel, IBM, Entasys, and North Carolina State University.

Nagu Dhanwada, senior technical staff member at IBM, chairs both the IEEE P2416 and Si2 Power Modeling Working Groups. According to Dhanwada, “This is a major contribution to the P2416 effort. As the first technology contribution to the P2416 Working Group, it’s expected to form a solid foundation for the resulting standard.”

“This new modeling technology is the first significant advance in power modeling in quite a long time” said Paul Traynar, technical fellow at ANSYS and a contributor to the Si2 effort.  “It will enable SoC designers to get consistent power estimates across design abstractions and especially early in the system design process.”

Julien Sebot, CPU architect at Intel and a member of the IEEE P2416 Working Group, added, “The Si2 contribution addresses the top priorities identified by the P2416 Working Group. The ability to create accurate, early estimates and to reuse and refine those estimates during the design process is essential in creating energy efficient systems-on-chip.  Si2’s contribution is a major step toward addressing that need.”

The IEEE-P2416 Working Group has already started reviewing the Si2 contribution.  In parallel, Si2 will further develop, for its members, the technology with expanded model semantics, proof-of-concept demonstrations, and reference design implementations.

This model and its use will be described as part of a DAC 2017 tutorial, “How Power Modeling Standards Power Your Designs,” Monday, June 19, 3:30-5:00 p.m., Room 18AB, Austin Convention Center.

For more information about this project, contact Jerry Frenkil at Jfrenkil@si2.org.  For information about the Si2 Low Power Working Group and other OpenStandards programs, visit http://www.si2.org/openstandards/.

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.  All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. Si2’s international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.

 

CHIP – PACKAGE CO – DESIGN ( OPEN3D ) Membership Agreement

Membership in the Si2 Chip-Package Co-Design (aka (Open3D))  requires agreement to the following documents.

First:   CHIP-PACKAGE CO-DESIGN (OPEN3D)MEMBERSHIP AGREEMENT

dtmc__dfmc__agreement

Second:  DTMC__DFMC__Operating_Policy-1.pdf:  Attachment C- Project IP Policy

dtmc__dfmc__operating_policy