Committee Corner: Aparna Dey, Cadence Design Systems

Recognizing Outstanding 
Si2 Committee Volunteers

aparnaAparna Dey chairs the Si2 Low Power Working Group and represents Cadence Design Systems in other Si2 activities and industry standards organizations. She also chairs the IEEE Electronic Design Symposium, an annual conference held in Monterey, Calif., and is the treasurer for IEEE Design Automation Standards Committee.

As the technical marketing group director in the Cadence Standards Group, Dey has focused on standards since 2012. It’s a role she finds both interesting and challenging.  “It’s exciting and rewarding to work together in the standards committee with our industry peers, including our competitors and customers, on interoperability solutions. However, showing our technical leadership while being mindful of what we contribute is a balancing act at times.”

Her 14 years at Cadence includes various engineering, methodology services, and technical marketing positions. She led the ASIC Alliances and SOC/IP Reuse Group in the Alliances and Methodology Services Division. That background provides a good match for her current role.  “Working with R&D architects to determine which standards are useful to which products requires broad exposure to all our marketing efforts.”

One side benefit to her current role is a reduced travel schedule, allowing her to spend more time with her third-grade daughter. “She loves math and science and hopes to be an engineer.”

Dey holds a Bachelor of Engineering degree in Electronics and Telecommunication from Netaji Subhas Institute of Technology, University of Delhi, India.

Member Spotlight: PhoeniX Software

By Twan Korthorst
Chief Executive Officer
PhoeniX Software
The Netherlands

With the applications space for integrated photonics expanding into traditional electronics areas, existing EDA and photonics design automation design methodologies must merge to provide the most efficient design flow.

As integrated photonics presents physical and analytical challenges that require unique methods not available in traditional electronic IC design tools, these need to be addressed. PhoeniX Software’s OptoDesigner Photonic IC phoenixdesign platform, with native curvilinear and all angle layout capabilities, can be used either stand-alone for photonic IC design or closely interfaced with EDA solutions to support the design of complex photonic-electronic ICs within an integrated environment.

Si2 Launches Effort to Develop New Integrated Circuit Power Modeling Technology

AUSTIN, Texas–Silicon Integration Initiative (Si2), an Austin-based integrated circuit research and development joint venture, has launched a project to help designers reduce power consumption, a growing challenge for most system-on-chip designs. The project will develop new power modeling technology to estimate power consumption more easily and more accurately throughout the design process, especially during the earliest stages.

The end result will be a new power modeling standard to reduce resources and costs needed to develop virtually every type of SoC.  Jerry Frenkil, director of OpenStandards, said that the Si2 Low Power Working Group, part of the newly restructured Si2 OpenStandards program, will lead this industry-wide effort.

“Every SoC design team is grappling with the continued need to reduce power consumption,” Frenkil said. “That’s especially true for mobile devices, but it’s also a concern throughout the electronics industry.  One way to accomplish this is through improved multi-level power modeling techniques that better predict SoC power and performance. Right now there’s no commonly accepted way to develop an accurate estimation of power consumption early in the design phase. This often leads to designs being power inefficient, performance constrained, or both.”

Frenkil said the standard will also “enable more efficient and reliable power analyses and optimizations since the same model will be used from system-level design through gate level implementation and all phases in between.”

The approved specification will be contributed to the IEEE P2416 Standards Working Group for industry-wide distribution. Nagu Dhanwada, senior R&D engineer at IBM, chairs both the IEEE P2416 and Si2 Low Power Modeling Working Groups.  “Since Si2 is an R&D joint venture, its members can work together to develop specifications, tests and proof-of-concepts with anti-trust protection. This specification will greatly accelerate standardization efforts within P2416, and testing prior to IEEE standardization will enable us to rapidly prove out the use of the new standard before it hits the street,” Dhanwada explained.

IEEE P2416 is an essential component of a coordinated IEEE effort focusing on system-level design. The IEEE 1801 standard currently expresses design intent.  It’s latest update, IEEE 1801-2015, includes support for power modeling.

John Biggs, co-founder and consultant engineer at ARM, chairs the IEEE 1801 Working Group. “Efforts of the Si2 Low Power Working Group will help the IEEE P2416 Working Group standardize the representation of power consumption data,” Biggs said. The fruits of this work, in combination with the new power modeling capability in IEEE 1801-2015, should greatly ease the challenging task of energy-aware system level design.”

The new Si2 model specification is expected to be completed in October. For more information about this project, contact Jerry Frenkil at  For information about the Low Power Working Group and other OpenStandards programs, visit

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.  All Si2 activities are carried out under the auspices of the The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. Si2’s international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.


Design Agility: The Solution to EDA Commoditization

By Marshall Tiner
Director, Production Standards
In a recent article, Randy Smith, vice president of Marketing for Sonics, pinpointed a problem confronting the EDA industry.
“The difference between IP and EDA doesn’t matter much anymore. It is all about design acceleration. “Where can we make a difference?” he added.
“The physical design flow has been commoditized at this point. It is hard to come up with anything that will make a big enough difference that you can add value. For system-level design, there is still plenty of room, but you will have to come up with some smart ideas.”
Moore says Moore’s law is “dead.”  Can we bet on technology not progressing? Or do we become agile and embrace the coming changes?
This problem is not unique to the EDA industry. It occurred in semiconductor manufacturing, computing and even
in software. It starts with new technology that rapidly improves over time, leading to cost competition and then commoditization. However, in every case, one important solution in these other industries had one similarity: standardization.
Semiconductor manufacturing went from high-volume, low mix to more complex high-mix, low-volume. Autonomously functioning agile manufacturing cells or modules were developed. The leverage point was standardization. Anything standardized could be reused, thus reducing costs.
Computers shrank from room-sized machines down to systems that were invisible to the human eye. With the free, standardized Linux platform we now reuse computers that run collectively as a “cloud.”
Software evolved from huge programs to collections of smaller, object-oriented languages that are easily shared and reused (yes, a type of standard). Programs can be quickly created using others as a foundation.
How does this apply to EDA? The total physical design cycle must be shortened to match current needs. We can’t redevelop entire checking decks between design passes as new rules are defined. Maybe we need a faster means of implementing new rules.
How can the EDA industry attain the agility it needs to grow?  The answer again focuses partially on a standard, one that supports agile rule checking-Si2 OpenAccess. Our oaScript, an extension to OpenAccess, allows writing rule checks quickly in a variety of languages, including perl, python, ruby and tcl.
Why restrict the rule authorship to EDA? Spread it around and do it faster. What if the technology team could code the rules? Or the physical designer?  Or enlist the program manager who set that ridiculous release date in the first place.
So, why not join the Si2 OpenAccess Coalition and use your company’s vote to drive the future the way you want it? Showcase and contribute some of your best “glue” code. Hear other solutions from the rest of the IC design community.

Why has IC physical design become commoditized? As time scales shrink and complexity increases, physical design cycles rely more on verification. A comprehensive set of rules need time to develop, and the technology changes occur simultaneously with the design. What’s needed is agility to repeat the design cycle quickly as new rules are invented.

Plans Begin for PDK Special Interest Group

Si2 is planning to launch its first special interest group, which will focus on process design kits. Ted Paone, interoperability standards architect, said the SIG will “refine the methodology to improve process data and create quality process design kits.” Special interest groups are open to all Si2 members. For more information contact Ted Paone,

What You Need to Know about R&D Joint Ventures

Si2 and other research and development joint ventures fill an important need for semiconductor companies competing in a fast-changing global market.

What are R&D joint ventures and what do you need to know about them?

The National Cooperative Research and Production Act of 1993 (NCRPA) is the fundamental law that defines R&D joint ventures and offers them a large measure of protection from federal antitrust laws. R&D joint ventures are formal agreements between two or more companies engaged in the research and development of technologies. They are proven tools for reducing design and production costs and speeding time-to-market.

The Federal Trade Commission and Department of Justice are the NCRPA watchdogs. They review applications for R&D joint ventures, approve or deny them, and monitor the operations of those approved, including any changes in membership.

Benefits of an R&D joint venture
Protection against legal challenges under Sherman and Clayton Antitrust laws is a significant benefit for members of NCRPA-approved, R&D joint ventures. In fact, no successful lawsuit has ever been filed against an NCRPA-approved R&D joint venture. Why? A “rule of reason” antitrust analysis shelters these protected collaborative activities. Without NCRPA protection, a more general “per se” viewpoint is used, where the behavior itself can be deemed to violate antitrust law. Also, if a violation occurs, the claimant can only receive actual damages, rather than treble damages available without NCRPA protection. This is a powerful deterrent against lawsuits.

Legal protections aside, R&D joint ventures can conduct a wide variety of activities, including:

  • perform theoretical analysis, experimentation or testing of basic engineering techniques
  • extend investigative findings into practical application for experimental and demonstration purposes
  • conduct experiments on models, prototypes and processes 
  • perform product certification testing
  • collect, exchange and analyze research or production information

Those types of activities mark a primary difference between an R&D joint venture and standards development organizations. SDOs can only perform voluntary, consensus standards activities, and though the NCRPA antitrust protection covers the SDO, it does not extend these protections to individual SDO members.

Any collaborative R&D activity done under the auspices and guidance of Si2 receives the same anti-trust protection. Si2 special interest groups, coalitions and working groups focus on solving industry problems, knowing they and their companies have the safety the NCRPA provides.

OpenStandards: A New Initiative for R&D Collaboration

OpenStandards, Si2’s newest member initiative, is the product of extensive member research and the core of a streamlined standards development process.

John Ellis, president and CEO, said market research and industry trends identified factors key to the creation of OpenStandards. “Speed and agility topped the list. The ability to quickly identify and create a needed standard are paramount.

“OpenStandards combines independent coalitions, technical advisory boards and new working into one, single-fee membership. Costs are reduced since companies can choose to participate in every activity, at any level, for one fee,” Ellis explained. “More than 90 percent of our members saw their dues decrease in 2016.” 

This was accomplished while maintaining the mandated safe-haven, anti-trust protection, he added. Activities currently part of OpenStandards are Chip-Package Codesign (3D), Design for Manufacturability, Low Power, OpenPDK, and Silicon Photonics.

Jerry Frenkil, director of OpenStandards, manages this program. Co-founder of Sente, he has more than 30 years’ experience in the semiconductor and EDA industries.

Si2 will explain the OpenStandards concept during a free webinar on Tuesday, January 26, 9-10 a.m. PST.