Geoffrey Coram Named New CMC Technical Advisor

Geoffrey J. Coram of Analog Devices is the new volunteer technical advisor for the Si2 Compact Model Coalition.  In this newly created position he advises the coalition on Verilog-A implementation for its standard compact models.

Over the past decade, the preferred language for development and implementation of compact models has shifted from C to Verilog-A. Recognizing the importance of the new language, the CMC officers created this position to assist model developers and help encourage best practices.

A senior member of the IEEE, Geoffrey has been an active CMC participant since 2002 and currently leads the CMC subcommittees on Verilog-A recommended practices and the MOS varactor model. In 2004, he led the efforts of the Accellera Verilog-AMS subcommittee to add compact modeling extensions to that modeling language in Language Reference Manual version 2.2.

Geoffrey joined the internal CAD development and circuit simulation group at Analog Devices after earning a Ph.D. from the Massachusetts Institute of Technology in 2000. His undergraduate degree is from Rice University.

Free Webinar for Si2 Members focuses on XML Schemas

Si2 announces the second in a series of member-only webinars focusing on XML–Introduction to XML Schemas.

XML schemas are the normative definitions of any XML-based standard. The schema defines the domain- specific vocabulary (DSV) and types of values in an XML database. The XML database must conform to its schemas, using the predefined elements and entering values that are compliant with the schema.

Session 1: Schema Syntax                           
Thursday, November 10
10:00 a.m.-11:00 a.m. PST
— What is a schema?
— Namespaces
— How to understand the contents of a schema
— Schema elements
Session 2:  Si2 OpenStandards Schemas
Thursday, November 17

10:00 a.m.-11:00 a.m. PST

— Installing Si2 OpenStandards schemas
— What is in each schema
— Examples of compliant XML databases

For more information click here.

Free Webinar for Si2 Members: Introduction to XML

Many Si2 OpenStandards are based on XML, the eXtensible Markup Language. XML files have a consistent syntax and, combined with the domain specific vocabulary defined in the Open Process Specification (OPS) schemas, succinctly capture the data used to model the IC fabrication process to the design tools.

The OPS XML database contains the constraints, layers, stacks, devices and rules that represent the fabrication process in a vendor-neutral format. This single source for the data is used to generate process design kits.

About the Course
This introductory course focuses on the XML file syntax that will help you create well-formed XML files. Through lecture, quizzes and labs, you will examine the syntax of XML elements and learn how to create, modify or read and understand an OPS XML file. We will explore the file format, elements and attributes, namespaces and connecting to schemas.

Prerequisites: A willingness to learn XML and an interest in OPS.

Course Outline

  1.   Exploring XML
    — XML editors
    — What is XML and why do we use it?
    — How do you use OPS XML?
    — What is a valid XML file?
  1.   XML File Format
    — XML prologue and comments
    — XML element declaration
    — Attributes
    — Sub-elements and content value
  1.   Namespaces and Schemas

The example used in the class is a single OPS XML hierarchy that will be used for future courses in this series.  A recording will be available on the Si2 Community web site.

Who Should Attend
Si2 member company employees who work with, create, edit or read XML data files are invited to attend this free webinar. 

Ted Paone
Si2 Interoperability Standards Architect

Ted Paone


Future Courses for Si2 Members

Si2 will offer additional XML classes  Announcements will be made by email and on our web site,

  • OpenStandard Schemas
  • XML editors
  • XML utilities
  • XML Python Parser
  • Writing ASCII technology files from OPS XML
  • Inputting comma separated value (CSV) files
  • Xinclude – Building a process database

Matt Wheaton Joins Si2 for OpenAccess Support

Matthew Wheaton, a software engineering professional whose experience includes more than 12 years at IBM, has joined Si2 as a senior programmer. His first responsibility is to take the lead on system builds and membership support of the Si2 OpenAccess database and scripting extensions, including oaScript.

While at IBM, Wheaton specialized in build, test, and delivery of EDA tools before moving into Front End tool development and management of the primitives library.

He has already built and configured a number of Linux hosts to compile oaScript and oaxPop, which were used to deliver the latest oaScript update (v.3.3).

A native of New England, Wheaton has a Bachelor of Arts degree in Computer Science from Western Connecticut State University.

Si2 Announces Board of Directors for 2016-2017

Si2 Members Meeting Set for Monday, June 6,
at the Design Automation Conference in Austin, Texas


AUSTIN, Texas–(BUSINESS WIRE)–The Silicon Integration Initiative (Si2) announced today the election of the 2016-17 board of directors. Board members will be introduced at the Si2 Member Meeting and Reception during the Design Automation Conference (DAC), June 6, 4:00-6:00 p.m., Austin Convention Center, Room A10.

New representatives on the Si2 board are:  Humair Mandavia, chief strategy officer, Zuken (6947: TYO) and Richard Trihy, director of Design Infrastructure, GLOBALFOUNDRIES.

Reelected board members are:

  • Tom Beckley, senior vice president, Custom IC & PCB Group, Cadence Design Systems (NASDAQ: CDNS)
  • David DeMaria, vice president, Corporate Marketing, Synopsys (NASDAQ: SNPS)
  • Keith Greene, distinguished member of the technical staff, Analog Technology Development, Texas Instruments (NASDAQ: TXN)
  • Rahul Goyal, vice president, Technology and Manufacturing Group and Director, EDA Business, Intel (NASDAQ: INTC)
  • Jong-Bae Lee, vice president, Design Technology Team, Samsung Electronics (OTC: SSNLF)
  • Suk Lee, senior director, Design Infrastructure Marketing Division, Taiwan Semiconductor Manufacturing Co. (NYSE: TSM)
  • Pravin Madhani, general manager, Place and Route Division, Mentor Graphics Corp. (NASDAQ: MENT)
  • Leon Stok, vice president, Electronic Design Automation Technologies, IBM (NYSE: IBM)
  • Nick Yu, vice president of Engineering, CDMA Technologies Division, Qualcomm (NASDAQ: QCOM)

“The board of directors plays a critical role in providing strategic direction for Si2,” said John Ellis, president and CEO, Si2.  “Technology advances from the semiconductor industry provide the foundation for ongoing innovation throughout the electronics industry. However, electronic system complexity continues to exponentially increase, at the same time that our industry is consolidating and overall growth has slowed,” he added.

“As a result, the need for efficient use of our members’ resources in collaborating on semiconductor and electronic system design tool interoperability has never been greater. To this end, our board determines the priorities for where Si2 resources must be focused,” Ellis said.

More information on the Si2 member-only meeting, including registration details, is found at:

About Si2:  Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.  All Si2 activities are carried out under the auspices of the The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. The Si2 international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.

Committee Corner: Aparna Dey, Cadence Design Systems

Recognizing Outstanding 
Si2 Committee Volunteers

aparnaAparna Dey chairs the Si2 Low Power Working Group and represents Cadence Design Systems in other Si2 activities and industry standards organizations. She also chairs the IEEE Electronic Design Symposium, an annual conference held in Monterey, Calif., and is the treasurer for IEEE Design Automation Standards Committee.

As the technical marketing group director in the Cadence Standards Group, Dey has focused on standards since 2012. It’s a role she finds both interesting and challenging.  “It’s exciting and rewarding to work together in the standards committee with our industry peers, including our competitors and customers, on interoperability solutions. However, showing our technical leadership while being mindful of what we contribute is a balancing act at times.”

Her 14 years at Cadence includes various engineering, methodology services, and technical marketing positions. She led the ASIC Alliances and SOC/IP Reuse Group in the Alliances and Methodology Services Division. That background provides a good match for her current role.  “Working with R&D architects to determine which standards are useful to which products requires broad exposure to all our marketing efforts.”

One side benefit to her current role is a reduced travel schedule, allowing her to spend more time with her third-grade daughter. “She loves math and science and hopes to be an engineer.”

Dey holds a Bachelor of Engineering degree in Electronics and Telecommunication from Netaji Subhas Institute of Technology, University of Delhi, India.

Member Spotlight: PhoeniX Software

By Twan Korthorst
Chief Executive Officer
PhoeniX Software
The Netherlands

With the applications space for integrated photonics expanding into traditional electronics areas, existing EDA and photonics design automation design methodologies must merge to provide the most efficient design flow.

As integrated photonics presents physical and analytical challenges that require unique methods not available in traditional electronic IC design tools, these need to be addressed. PhoeniX Software’s OptoDesigner Photonic IC phoenixdesign platform, with native curvilinear and all angle layout capabilities, can be used either stand-alone for photonic IC design or closely interfaced with EDA solutions to support the design of complex photonic-electronic ICs within an integrated environment.

Si2 Launches Effort to Develop New Integrated Circuit Power Modeling Technology

AUSTIN, Texas–Silicon Integration Initiative (Si2), an Austin-based integrated circuit research and development joint venture, has launched a project to help designers reduce power consumption, a growing challenge for most system-on-chip designs. The project will develop new power modeling technology to estimate power consumption more easily and more accurately throughout the design process, especially during the earliest stages.

The end result will be a new power modeling standard to reduce resources and costs needed to develop virtually every type of SoC.  Jerry Frenkil, director of OpenStandards, said that the Si2 Low Power Working Group, part of the newly restructured Si2 OpenStandards program, will lead this industry-wide effort.

“Every SoC design team is grappling with the continued need to reduce power consumption,” Frenkil said. “That’s especially true for mobile devices, but it’s also a concern throughout the electronics industry.  One way to accomplish this is through improved multi-level power modeling techniques that better predict SoC power and performance. Right now there’s no commonly accepted way to develop an accurate estimation of power consumption early in the design phase. This often leads to designs being power inefficient, performance constrained, or both.”

Frenkil said the standard will also “enable more efficient and reliable power analyses and optimizations since the same model will be used from system-level design through gate level implementation and all phases in between.”

The approved specification will be contributed to the IEEE P2416 Standards Working Group for industry-wide distribution. Nagu Dhanwada, senior R&D engineer at IBM, chairs both the IEEE P2416 and Si2 Low Power Modeling Working Groups.  “Since Si2 is an R&D joint venture, its members can work together to develop specifications, tests and proof-of-concepts with anti-trust protection. This specification will greatly accelerate standardization efforts within P2416, and testing prior to IEEE standardization will enable us to rapidly prove out the use of the new standard before it hits the street,” Dhanwada explained.

IEEE P2416 is an essential component of a coordinated IEEE effort focusing on system-level design. The IEEE 1801 standard currently expresses design intent.  It’s latest update, IEEE 1801-2015, includes support for power modeling.

John Biggs, co-founder and consultant engineer at ARM, chairs the IEEE 1801 Working Group. “Efforts of the Si2 Low Power Working Group will help the IEEE P2416 Working Group standardize the representation of power consumption data,” Biggs said. The fruits of this work, in combination with the new power modeling capability in IEEE 1801-2015, should greatly ease the challenging task of energy-aware system level design.”

The new Si2 model specification is expected to be completed in October. For more information about this project, contact Jerry Frenkil at  For information about the Low Power Working Group and other OpenStandards programs, visit

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.  All Si2 activities are carried out under the auspices of the The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. Si2’s international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.


Design Agility: The Solution to EDA Commoditization

By Marshall Tiner
Director, Production Standards
In a recent article, Randy Smith, vice president of Marketing for Sonics, pinpointed a problem confronting the EDA industry.
“The difference between IP and EDA doesn’t matter much anymore. It is all about design acceleration. “Where can we make a difference?” he added.
“The physical design flow has been commoditized at this point. It is hard to come up with anything that will make a big enough difference that you can add value. For system-level design, there is still plenty of room, but you will have to come up with some smart ideas.”
Moore says Moore’s law is “dead.”  Can we bet on technology not progressing? Or do we become agile and embrace the coming changes?
This problem is not unique to the EDA industry. It occurred in semiconductor manufacturing, computing and even
in software. It starts with new technology that rapidly improves over time, leading to cost competition and then commoditization. However, in every case, one important solution in these other industries had one similarity: standardization.
Semiconductor manufacturing went from high-volume, low mix to more complex high-mix, low-volume. Autonomously functioning agile manufacturing cells or modules were developed. The leverage point was standardization. Anything standardized could be reused, thus reducing costs.
Computers shrank from room-sized machines down to systems that were invisible to the human eye. With the free, standardized Linux platform we now reuse computers that run collectively as a “cloud.”
Software evolved from huge programs to collections of smaller, object-oriented languages that are easily shared and reused (yes, a type of standard). Programs can be quickly created using others as a foundation.
How does this apply to EDA? The total physical design cycle must be shortened to match current needs. We can’t redevelop entire checking decks between design passes as new rules are defined. Maybe we need a faster means of implementing new rules.
How can the EDA industry attain the agility it needs to grow?  The answer again focuses partially on a standard, one that supports agile rule checking-Si2 OpenAccess. Our oaScript, an extension to OpenAccess, allows writing rule checks quickly in a variety of languages, including perl, python, ruby and tcl.
Why restrict the rule authorship to EDA? Spread it around and do it faster. What if the technology team could code the rules? Or the physical designer?  Or enlist the program manager who set that ridiculous release date in the first place.
So, why not join the Si2 OpenAccess Coalition and use your company’s vote to drive the future the way you want it? Showcase and contribute some of your best “glue” code. Hear other solutions from the rest of the IC design community.

Why has IC physical design become commoditized? As time scales shrink and complexity increases, physical design cycles rely more on verification. A comprehensive set of rules need time to develop, and the technology changes occur simultaneously with the design. What’s needed is agility to repeat the design cycle quickly as new rules are invented.