Jushan Xie New Vice-Chair of Si2 Compact Model Coalition

Dr. Jushan Xie, senior software architect at Cadence Design Systems, is the new vice-chair of the Si2 Compact Model Coalition. He joined Cadence in January 1999, working with SPICE (Simulation Program with Integrated Circuit Emphasis) model extraction tools and later SPICE modeling for circuit simulation. He is currently in charge of Spectre SPICE modeling and reliability modeling. He received a Ph.D. in Physics from University of Saarland, Saarbruecken, Germany, in 1996, and a second Ph.D. in applied mathematics from Louisiana Tech University, in 1999.

The Si2 Compact Model Coalition is a collaborative group that develops and maintains cost-saving SPICE models for IC design.

Empyrean Software, Qorvo Join Si2 Compact Model Coalition

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Empyrean Software, Qorvo Join Si2 Compact Model Coalition

 

For Immediate Release

 

AUSTIN, Texas—Empyrean Software and Qorvo have joined the Silicon Integration Initiative (Si2) Compact Model Coalition (CMC), a collaborative group that funds the standardization of cost-saving SPICE models for integrated circuit designs.

They join 30 other companies that increasingly rely on the use of industry-standard SPICE models (Simulation Program with Integration Circuit Emphasis) to simulate the performance of new and enhanced chip designs prior to manufacturing. As a research and development joint venture focused on IC design tool operability standards, Si2 provides a legally protected environment for its members to share resources for funding SPICE model standardization.

“SPICE device models are equations that express transistor function. These fundamental building blocks provide IC designers with the ability to simulate and validate design function and performance before entering the capital-intensive phase of manufacturing,“ said John Ellis, Si2 president and CEO. “To reduce R&D costs and increase simulation accuracy, the semiconductor industry has turned to the CMC to pool resources and fund the standardization of best-of breed models.

“Once the standard models are proven and accepted by CMC, they are incorporated into design tools providing cross-correlation between simulators and widely used by the semiconductor industry. The standard models have been developed, and are refined and maintained, under direction and funding by the CMC, by leading universities and national labs,” Ellis explained.

Steve Yang, CEO of Empyrean Software, said “As designs move to advanced processes, the simulation models provided by CMC are vitally important for our tools to provide accurate results and validate designs before they are manufactured.  As the largest China EDA software supplier, Empyrean’s EDA tools cover complete custom AMS design flow: schematic entry, layout editing, circuit simulation, DRC/LVS, and RC extraction.”

For more information about the CMC visit http://www.si2.org/cmc/.

 

About the Silicon Integration Initiative (Si2)

Si2 is a leading research and development joint venture that provides standard interoperability solutions for IC design tools. Its primary products include OpenAccess, the world’s most widely used, open reference database for IC design, with a supporting standard APA. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

 

Media Contact:

Terry Berke
512-917-1358
tberke@si2.org

Si2 Recruiting Engineering Students for IC Design Program

 

Silicon Integration Initiative (Si2) is recruiting engineering students for its University Partner Network, a program that offers real-world, electronic design automation job experience.

Si2 is the industry’s most experienced, federally registered research and development joint venture for the collaborative development of standard, interoperable EDA software.  Marshall Tiner, director of Production Standards, who oversees the University Partner Network, said volunteer partners are vital contributors to a variety of R&D projects.

“Students accepted into the program work hand-in-hand with IC design experts and design tool developers from our global members,” Tiner said.  “They represent leading semiconductor manufacturers, fabless companies and EDA tool suppliers. “The University Partner Network has proven to be a springboard into the EDA Industry, for partners whose work with us had led to full-time employment.  Partners strengthen their resumes and broaden their network with prospective employers.  Employers benefit also, by identifying and working with prospective employees.”

Partners must be currently enrolled in an undergraduate or graduate engineering degree program.  They should have some programming experience and a general understanding of semiconductor design.

For more information to to apply for the program, visit http://www.si2.org/si2-eda-university-partner-network/

New Si2 Working Group to Develop Unified Power Model for System-Level IC Design

AUSTIN—Silicon Integration Initiative, Inc. (Si2), a research and development joint venture focused on integrated circuit design tool interoperability standards, has launched a System Level Power working group to create the Si2 Unified Power Model (UPM), a standard which will strengthen power management in system-level IC design.

Jerry Frenkil, director of the OpenStandards Coalition, which incubates new Si2 standards, said development of the Si2 UPM is part of the industry’s ongoing effort to improve energy and power efficiency throughout the system-on-a-chip development flow, with a focus on system design.

“Energy efficiency is a growing and costly constraint in integrated circuit design,” Frenkil explained.  “There’s currently no standard, single model to represent power data at the system level across a range of process, voltage, and temperature (PVT) points.  Different, often inconsistent models are currently used in each of the three major stages of IC design:  system design, register transfer level (RTL) design, and implementation.  None of those models currently support voltage or temperature dependencies.  The Si2 UPM addresses those issues.”

When completed, the Si2 UPM will enable faster turnaround time for system-level power and thermal analyses, as well as reduce resources and costs incurred in power model generation, Frenkil said.  The approved specification, including the capability to supply power data to IEEE 1801/UPF power state models, will be contributed to the IEEE P2416 Working Group for ongoing maintenance and industry-wide standardization. IEEE P2416 supports the ability to develop accurate, efficient and interoperable power models for complex, integrated circuit designs.

Si2 members participating in the working group are ANSYS (NASDAQ: ANNS), Cadence Design Systems (NASDAQ: CDNS), IBM (NYSE: IBM), Intel (NASDAQ: INTC) and Entasys.

The Si2 UPM will benefit the three major constituencies to the IC design ecosystem:

  • For IP providers:
    • A system-level power data model companion for the IEEE 1801 (UPF) power state model
    • reduced time and resources for model and library generation and support.
  • For system and SoC architects
    • true system-level modeling that eliminates the need for gate-level netlists.
    • faster turn-around time for system-level power and thermal analyses
    • model consistency across abstractions
  • For EDA providers
    • New, non-cannibalistic product and solution opportunities

For information about the new Si2 UPM working group or other Si2 OpenStandards projects, contact Jerry Frenkil, jfrenkil@si2.org.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust law.

Have Ideas on Improving the IC Design Ecosystem?

Si2 is seeking industry input on an international effort to identify and address ways to streamline and improve the IC design ecosystem. The finished product will be a DAC 2018 white paper whose contents will present an industry consensus on specific ways the industry can manage the rising costs of more complex designs and smaller geometries.

We’re looking for comments and suggestions on specific design concerns to include in an industry survey whose results will provide data for the white paper. IC designers and engineers can submit survey questions for consideration at https://lnkd.in/eJGgVQR.

If you have questions about the survey or white paper contact Ted Paone, tedp@si2.org.

Prashant Varshney of Mentor Graphics Elected to Si2 OpenAccess Board

Prashant Varshney is Mentor Graphics’ newly elected representative on the Si2 OpenAccess Coalition board of directors and OpenAccess Change Team.

Prashant is the group director of Product Marketing at Mentor, where he oversees marketing efforts for the new design platform for developing mixed-signal IoT SoCs, senors, MEMS, silicon photonics and industrial IoT applications. Previously at Mentor he led product management, development and deployment for various ASIC design products in the physical design, formal verification and static timing analysis space, such as Olympus, Nitro, Optimus and FormalPro.

Prashant holds an MSEE from Stanford University.

The Si2 OpenAccess Coalition board oversees operational decisions for OpenAccess, the world’s most widely used, open reference database for IC design with a supporting standard API. The change team manages API modifications and database implementation.

Si2 Launches Effort to Improve IC Ecosystem

Si2 Launches Effort to Improve IC Design Ecosystem

New Special Interest Group Will Present Recommendations at DAC 2018

Si2 is seeking industry input on an international effort to identify and address ways to streamline and improve the IC design ecosystem. The finished product will be a DAC 2018 white paper whose contents will present an industry consensus on specific ways the industry can manage the rising costs of more complex designs and smaller geometries.

Ted Paone, Si2 interoperability standards architect, said the first step in the process was the formation of the Si2 Design Ecosystem Special Interest Group (SIG), which will write and distribute an industry-wide survey identifying areas of concern. The survey will launch in March 2018. Intel, Cadence Design Systems, Micron, Samsung, IBM and PDF Solutions are charter members of the SIG, which will investigate the impact of current issues in design and the expectations of future design requirements including performance and interoperability improvements to design data bases and scripting languages.

IC designers and engineers can submit survey questions for consideration at https://www.surveymonkey.com/r/9NSZCLC.

“We’re asking for the industry to help identify their specific design concerns so we can incorporate them into our survey,” he explained. “These are the people whose day-to-day activities are complicated by the need to create successful silicon while dealing with more and more complex processes, larger designs, new security and traceability issues, and emerging technologies such as chiplets, photonic elements and three-dimensional packaging.”

For information about the Si2 Design Ecosystem SIG, contact Paone, tedp@si2.org.  Information about joining the SIG is available at www.si2.org.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust law.

Members Invited to Si2 OpenAccess Annual Meeting

The Si2 OpenAccess Coalition will hold its annual meeting on Friday, October 27, 9:00 a.m. – 10:45 a.m. (PST). Meeting locations are:

  • Synopsys, Mountain View, California
  • Si2, Austin, Texas
  • IBM, Poughkeepsie, New York

Members can also attend via WebEx.

For details and registration visit:  http://www.si2.org/oa-annual-meeting/

Si2 University Partner Network Helps Launch EDA Career

It didn’t take long for Sushmitha Moturi to successfully leverage her volunteer experience in the Si2 University Partner Network. After earning a graduate in electrical engineering at the University of Florida, Sushmitha joined Qualcomm as an embedded software stability engineer. She credits the next network and its industry mentors for helping launch her EDA career.

“Volunteering with Si2 was a great experience and certainly helped me in my job search,” Sushmitha said. “My focus with Si2 was testing the OpenAccess Track Pattern Extension. That helped me hone my programming and debugging skills, which are essential in my job at Qualcomm.  I also learned a lot from my Si2 mentors, who were professionals in the field.”

Si2 is the industry’s most experienced, federally registered, research and development joint venture for the collaborative development of standard, interoperable, EDA software. The Si2 University Partner Network connects qualified engineering student-partners to their future employers in a program that offers real-world, electronic design automation job experience. Partners strengthen their resumes and broaden their network with prospective  employers, while employers identify and work with prospective employees.

The network is currently accepted applications for new partners.  For complete information visit http://www.si2.org/si2-eda-university-partner-network/