Si2 Compact Model Coalition Releases BSIM-CMG SPICE Model for Advanced IC Designs

CMC Members Benefit from 18-Month Early Access to New Standard Model

AUSTIN, Texas — The Si2 Compact Model Coalition has released the latest version of BSIM-CMG FinFET, a standard compact SPICE model developed by researchers at the University of California, Berkeley, in conjunction with 20 partners from many of the industry’s leading semiconductor companies.

CMC is a collaborative industry group that standardizes SPICE (Simulation Program with Integration Circuit Emphasis) device models.

John Ellis, Si2 president and CEO, said FinFET is the transistor design that powers the industry along Moore’s Law to advanced leading-edge integrated circuits, including the latest 7nm chips used in every new smartphone, tablet, server, and personal computer. “The industry-standard SPICE model for FinFET is the 3D multi-gate transistor, a critical part of the ecosystem. Its sophistication required a cross-industry team to bring this model to fruition,” Ellis said.

“FinFET” refers to a visual description of a multi-gate, non-planar transistor. In IC design, field-effect-transistor gates wrap around the three sides of a vertical, fin-like channel, creating conducting channels on all sides of the structure. FinFET was named by Dr. Chenming Hu, a National Medal of Technology and Innovation recipient and professor emeritus in the Electronic Engineering and Computer Science Department at UC Berkeley.

“The model updates in the new release (111.0.0) are important refinements and fixes,” stated CMC BSIM-CMG working group chair, Richard Williams. “This new release will benefit all BSIM-CMG users in its myriad applications.” Through the CMC—­and working under Si2’s anti-trust umbrella as a collaborative R&D joint venture—university researchers, simulation software suppliers, fabless, foundry and integrated device manufacturers team up to produce a variety of industry-standard models. CMC members have immediate access to new standards, while new standards are released to the public 18 months after initial release.

Dr. Harshit Agarwal, a post-doctoral developer at UC Berkeley states, “CMC provides a tie to the industry that keeps us in close touch with the customer’s needs. Without CMC there’s no shared funding to support our model standardization, and the data, testing, and feedback on model performance would have to be sought after on a company-by-company basis. Together we are all much more intelligent and customers can cooperatively prioritize their requested features and bug fixes. Beyond this, the quality assurance program provided by CMC ensures our model, and the simulator provider’s implementations, perform at their absolute best for the designers.”

Dr. Peter Lee, CMC chair, agreed and added, “It has been two-and-a-half years since the last major BSIM-CMG update, which is equivalent to a semiconductor generation or two. This new version implements 25 enhancements and 13 bug fixes which improve accuracy, convergence, and performance when compared to the previous version. These changes can have important implications in shortening design time and ensuring first silicon success for a wide variety of products.”

Enhancements include improvements to the thermal noise model and the introduction of gate current scaling factors. Bug fixes include corrected parameter range, and use of macros instead “ifdef’s”, making the code even more robust.

 

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

Microsoft, GLOBALFOUNDRIES Join Si2 OpenAccess Coalition

Growing Membership Shows Ongoing Vertical Integration in IC Design

Austin, Texas—Microsoft Corporation and GLOBALFOUNDRIES have joined Silicon Integration Initiative’s OpenAccess Coalition, a diverse group of international semiconductor companies that support the OpenAccess design database application programming interface.

OpenAccess, which was introduced in 2002, is the most widely used IC design database and is currently supported by its 43 members, representing semiconductors manufacturers and foundries, fabless companies, EDA software providers and systems houses. The OpenAccess database provides EDA software tools with immediate design flow interoperability, saving members time and money.

John Ellis, Si2 president and CEO, said that the recent addition of Microsoft—and Google last year—illustrates the continuing trend of IC design vertical integration. He cited a recent Si2 industry survey which showed “that more than 80 percent of end users develop specialized, internal design tools. OpenAccess allows these home-grown tools to fit into the company’s own, optimized design flow, integrating the best-in-class EDA tools without sacrificing interoperability or performance.

“These end-users are often most interested in the OpenAccess scripting-language interface, which gives engineers direct access into their OA-based design through, for example, the Python programming language,” Ellis said. “This makes their design directly accessible from the console, or rapidly prototyped scripts. Python is well-known and widely adopted by programmers, and has many libraries and tools available, including popular AI development toolkits. The new code release supports these and provides a path toward developing machine-learning-based EDA tools which can make use of the OA database for training.”

Si2 recently introduced OpenAccess Data Model 6, the first major code revision since 2014. DM6 features oaPartitions, a new addition which allows multiprocessing capability to be applied simultaneously to smaller, partitioned regions in large chip designs. Early-stage performance benchmarking by Dr. Rhett Davis from N.C. State University, which was presented at the recent Design Automation Conference, showed under certain circumstances a more than 10x processing speed improvement over the prior version of OpenAccess. DM6 provides a path to higher-efficiency design. Its multiprocessing capability enables cloud-centric design flows for EDA tools which are based on the OpenAccess database.

IEEE Approves New Power Modeling Standard. 2416-2019 Built on Si2 Unified Power Model

AUSTIN, Texas–Silicon Integration Initiative has announced that its Unified Power Model, developed with major contributions from IBM and GLOBALFOUNDRIES, has been approved as IEEE 2416-2019, a new Standard for Power Modeling to Enable System Level Analysis, which complements UPF/IEEE 1801-2018 Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems.

Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

UPM/IEEE 2416-2019 provides a rich set of power modeling semantics enabling system designers to model entire systems with great flexibility. It supports power modeling from abstract design description all the way to gate level implementation providing data consistency from earliest architectural explorations to final power verification.

“We view UPM/IEEE 2416 as a major step forward for low power design,” commented Dr. Nagu Dhanwada of IBM, chair of the IEEE 2416 and the Si2 UPM Working Groups.

“The foundation of the UPM/IEEE 2416-2019 standard originated in IBM and has been successfully used in power sign-off of several generations and families of IBM microprocessors. Concepts like multi-level, state-based modeling and efficient, expressive semantics in UPM/IEEE 2416-2019 support constructing accurate and standardized power models for IP blocks. This enables SoC designs to be energy efficient from the ground up, a key reason companies will use 2416-2019 to upgrade modeling, analysis and sign-off flows,” stated Dr. Dhanwada.

Si2 UPM is a product of the Si2 OpenStandards Coalition, an R&D incubator which rapidly seeds and prototypes potential new EDA software tool interoperability standards. “The target of this development and subsequent standardization was an efficient and flexible mechanism for the specification and interchange of consistent power models throughout a project’s lifetime, from system design to manufacturing, especially for IP blocks and chiplets,” said Jerry Frenkil, Si2 director of OpenStandards. “This work led to significant advances in power modeling, including contributor and multi-level modeling, both of which are included in the 2416-2019 standard.”

A prototype power tool, upmPowerCalc, was built to prove the new concepts from end-to-end, both accelerating the delivery of a ready-to-implement standard and providing OpenStandards members with tools to aid in their own implementation.” The Si2 work was supported by the UPM Working Group consisting of ANSYS, IBM, Intel, Cadence, Entasys, and Thrace Systems.

Power contributors are Process, Voltage, and Temperature independent proxies for power. This PVT independence enables the late binding of PVT conditions at simulation run time, enabling power analysis at various PVT corners without requiring new libraries. Multi-level models provide multiple model views, or interfaces, to access the same power data. With multi-level construction, a single model provides consistent data for both system-level abstract simulations and bit-level simulations with RTL or gates.

“These advancements, along with UPM’s semantic expressiveness, deliver multiple benefits for design organizations” Frenkil explained. “System architects and SoC designers can model entire systems at a variety of PVT points with great flexibility. Power can be modeled in UPM using scalars, tables, expressions, and contributors, as well as expressions referencing contributors.”

UPM’s expressiveness also provides major benefits for IP developers. The use of power contributors leads to significant productivity gains since far fewer models and libraries are needed with UPM’s PVT independence. In addition, the models are abstract black boxes – functionality cannot be reverse-engineered from the power models.

Model interoperability and consistency with UPF/IEEE 1801 were identified early on as key goals in support of increasing emphasis on system level design. “IEEE 2416 provides a standardized interoperable system-level power model that is an essential piece of the foundation of an emerging industry-scale chiplet ecosystem” commented Ramune Nagisetty, senior principal engineer and director of Process and Product Integration at Intel Corporation.

“Energy-aware, system-level design can be a challenging task,” added John Biggs, chair of the IEEE P1801 Working Group, and distinguished engineer and co-founder of Arm. “With this new standard, designers will be better enabled by having access to semiconductor IP delivered with both IEEE 1801 power state models and IEEE 2416 power data models.”

For design automation groups, UPM provides an industry-standard format for both internal and external IP. This common format saves resources and time as there is no need to support or translate external proprietary formats. UPM also reduces reliance on internal proprietary formats, a long-standing design obsolescence trap.

An EDA startup, Thrace Systems, is planning to add IEEE 2416 support to its products. “UPM/IEEE 2416 is an important new standard. Its rich modeling semantics provide our power analysis platform with the solid infrastructure needed for comprehensive system level analysis,” commented David Ratchkov, Thrace Systems founder and CEO.

The P2416 Working Group was led by IBM, Si2, and Cadence, with active support from Intel and Arm.

For more information contact Jerry Frenkil at jfrenkil@si2.org.

Rahul Goyal of Intel Re-elected Board Chair of Silicon Integration Initiative

AUSTIN, Texas — Rahul Goyal of Intel has been reelected to a one-year term as board chair of Silicon Integration Initiative, a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. The election was held during Si2’s board meeting at the recent Design Automation Conference.

Other companies represented on the Si2 board are: ANSYS, Cadence Design Systems, GLOBALFOUNDRIES, Google, IBM, Qualcomm Technologies, Samsung, Siemens–a Mentor Business, Synopsys and Texas Instruments.

John Ellis, Si2 president and CEO, said Goyal’s reelection “will assure leadership continuity as we expand support for our members into such advanced technologies as artificial intelligence, machine learning, and design in the cloud.”

A member of the Si2 board since 2003, Goyal is vice president, Technology and Manufacturing Group and director, Research and Development Strategic Enabling for Intel. He has global responsibility for strategic sourcing, supply chain strategy, industry relations, ecosystem development, strategic collaborations, data analytics, and capacity management related to product development across Intel’s broad product portfolio. This includes software, system and semiconductor intellectual property, product development outsourcing services, electronic measurement solutions, Electronic Design Automation software, prototyping and verification products used in all aspects of product design, validation and technology development.

Goyal joined Intel in 1989 and has held various technical and management positions in software engineering and technology development. His previous roles there include engineering director in the Design and Technology Solutions Group, director of the integrated silicon technology roadmap development in the Microprocessor Products Group, and senior engineering manager of mask operations. Goyal holds a bachelor’s degree in electrical and electronics engineering from Birla Institute of Technology and Science in Pilani, India, and a master’s degree in computer engineering from Syracuse University in New York.

Si2 Elects Board Members for 2019-2020

Silicon Integration Initiative, a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools, announced today the election of the 2019-2020 board of directors. Board members will be introduced at the Si2 Member Meeting and Reception during the Design Automation Conference, June 3, 4:00 – 5:30 p.m., Las Vegas Westgate Hotel, Ballroom F.

Joining the Si2 Board this year is:

  • ANSYS—Vic Kulkarni, vice president and Chief Strategist, ANSYS Inc.

Re-elected board members are:

  • Cadence Design Systems—Stanley Krolikoski, fellow, Strategic Alliances
  • GLOBALFOUNDRIES—Richard Trihy, vice president, Design Enablement
  • Google—Roger Carpenter, Hardware Engineer
  • IBM—Leon Stok, vice president, Electronic Design Automation Technologies
  • Intel—Rahul Goyal, vice president, Technology and Manufacturing Group and director, Research and Development Strategic Enabling
  • Mentor, a Siemens Business—Mick Tegethoff, director of Product Marketing for Analog/Mixed-Signal/RF IC Verification Solutions
  • Qualcomm Technologies—Udi Landen, vice president of Engineering
  • Samsung Electronics—Seungbum Ko, vice president, Electronics Design Technology Team
  • Synopsys—David DeMaria, vice president, Corporate Marketing
  • Texas Instruments—Keith Green, distinguished member of the technical staff, Analog Technology Development

Details on the Si2 Member Meeting and Reception and other Si2 DAC activities are available at http://www.si2.org/dac_2019/

Si2 Announces Winners of Inaugural Power of Partnerships Awards

Si2 Announces Winners of Inaugural Power of Partnerships Awards

Engineers from Intel, Samsung and Synopsys Honored

AUSTIN, Texas – Semiconductor design experts from Intel, Samsung and Synopsys are winners of the first annual Si2 Power of Partnerships award which recognizes the Si2 group or committee that has made the most significant contributions to the success of electronic design automation industry.

Volunteers of the Si2 OpenAccess oaScript Working Group were the winners of a competition between committees from each of three Si2 coalitions:  OpenAccess, Compact Model, and OpenStandards.  Key contributors from the oaScript Working Group will be recognized during the Si2 Annual Member Meeting Reception at the Design Automation Conference in Las Vegas, Monday, June 3, 4:00 – 5:30 p.m. Las Vegas Westgate Hotel, Ballroom F.

Honorees from the oaScript Working Group are:

  • Rudy Albachten, oaScript Working Group Chair; Co-Chair, OpenAccess Coalition; and Principal Member of the Technical Staff, Intel
  • James D. Masters, Engineering Manager, Intel
  • Cory Krug, Senior Staff Engineer, Samsung
  • Christian Delbaere, Senior Staff Research and Development Engineer, Synopsys

Marshall Tiner, Si2 director of Production Standards, said the oaScript Working Group plays a major role in expanding the functionality of OpenAccess, the world’s most widely used standard API and reference database for integrated circuit design. “This group has brought EDA development capabilities directly to the designers. EDA startups and design groups within end-user companies use it for rapid development of production design tools that strengthen OpenAccess’ relevance,” Tiner said.

“The use of scripting languages, such as Python, to directly access the OpenAccess database is a powerful feature. Turn-around time for creating and modifying scripted code is very fast, and almost all new university graduates are well-versed in one or more scripting languages. Beyond this, there are a number of additional packages available, such as the powerful Polygon Operators extension which relies on oaScript. Access to AI tools, such as TensorFlow, which is built on Python, is now accessible to our users,” Tiner added.

Each Si2 coalition nominated one team for the inaugural award, which spotlights the essential role that teams and individual member volunteers play in Si2’s continuing success:

Runners up in 2019 were:

Compact Model Coalition:  Gallium Nitride High Electron Mobility Transistor (HEMT) Model Working Group, which released two standard models in 2018, culminating a multi-year effort by members and developers.

OpenStandards Coalition:  Unified Power Model Working Group developed several versions of a specification for system-level power modeling focused on IP blocks of arbitrary complexity.

James Masters of Intel to Lead Si2 Extensions Steering Group

AUSTIN, Texas — James Masters of Intel has been elected chairman of the Silicon Integration Initiative Extensions Steering Group, a team of industry volunteers that creates productivity enhancements to OpenAccess, the world’s most widely used standard API and reference database for integrated circuit design. Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

The ESG was launched in 2011 to increase the ease and pace of adding OpenAccess functionality, through extensions to the database, without affecting the consistency and stability of the core API standard and its associated reference implementation.

Marshall Tiner, Si2 director of Production Standards, said the ESG is responsible for reviewing and approving new features and capabilities for the API which are not part of the regular development process. “This has allowed for more flexible development in the OpenAccess environment to meet ever-changing market requirements,” Tiner said.

“James has played a major role in the ESG since its creation. His work with Si2 is an example of his decade-long advocacy for standards to streamline the design flow and maximize productivity and reuse,” Tiner added. “That includes guidance developing the ESG’s major subgroups, oaScript and oaxPop. oaScript provides scripting-language access into the database for Python, tcl, Ruby, and perl, allowing rapid development of user-created tools. oaxPop is the polygon operators extension that makes use of oaScript to provide a Python-based, rapid polygon analysis package for users.”

A 23-year Intel veteran, Masters currently manages an Intel team that enables custom layout capabilities of process nodes, including development of process design kit content. He works with EDA suppliers to improve the overall custom layout of the EDA ecosystem.

Si2 Names Dr. Rhett Davis Technical and Education Advisor

AUSTIN, Texas — Rhett Davis, professor of Electrical and Computer Engineering at North Carolina State University, has been named Technical and Educational Advisor for Silicon Integration Initiative. Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

“This new position expands Davis’ reach and impact on the semiconductor industry,” said John Ellis, Si2 president and CEO.  “His experience with the Si2 OpenAccess database and in artificial intelligence and machine learning will be brought to bear on expanding the ecosystem surrounding our newly upgraded version of OA. The new OA release will greater support high-performance, partitioned, multithreaded AI EDA applications. Dr. Davis’ expertise will assist Si2 and its members in bridging the gap between visionary research and real-world, high-performance, AI applications.”

In this expanded advisory role Davis, who has a doctorate in electrical engineering from the University of California at Berkeley, will continue consulting for Si2 in the areas of system-level power modeling and compact modeling. He has been instrumental in prototyping early-stage implementation of the newly created Unified Power Model now being standardized by Si2 within IEEE.  In the Si2 Compact Model Coalition, Davis has helped the Open Model Interface Working Group rearchitect the TSMC-contributed interface, which allows users to modify model parameters during circuit simulation.

Davis will also support the five university members of the OpenAccess Coalition: North Carolina State, University of Florida, State University of New York, Stanford University and Einhoven University of Technology (Netherlands.)  University members have direct use of the OpenAccess database, which streamlines the path to developing design production tools.

Dr. Davis joined North Carolina State University in 2002 as an assistant professor and became professor in 2008. He received the National Science Foundation Faculty Early Career Development award in 2007 and the Si2 Distinguished Service Award in 2012 development of standards for electronic design automation, and the FreePDK open-source, predictive process design kit.

He has been an IEEE member since 1993 and became a senior member in 2011. He has published over 50 scholarly journal and conference articles

Dr. Davis’ research is centered on developing methodologies, CAD tools, and circuits for systems-on-chip in emerging technologies. His interests include 3DIC design and low-power and high-performance circuit design for digital signal-processing and embedded systems.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. Its activities include support of OpenAccess, the world’s most widely used standard API and reference database for integrated circuit design. All Si2 activities are carried out under the auspices of the The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws

Si2 Welcomes New Members: Mythic and Thrace Systems

Si2 welcomes its newest members

OpenAccess Coalition — Mythic
www.mythic-ai.com

 

 

OpenStandards Coalition — Thrace Systems
www.thracesystems.com

Qualcomm, Samsung Name New Si2 Board Members

AUSTIN, Texas—Qualcomm Incorporated and Samsung Electronics have named two executives to join the Silicon Integration Initiative board of directors.  Si2 is a global research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

Udi Landen is Vice President of Engineering at Qualcomm Technologies, Inc.  In his current role, Landen provides technical, management and business leadership for engineering teams at various international sites that focus on mobile and computing design enablement and CAD methodology automation roadmaps.  Prior to joining Qualcomm in 2013, Landen held executive and leadership roles at Altera Corp., Mercury Interactive and Cadence Design Systems.  He is a graduate of the Technion, Israel Institute of Technology.

 

Seungbum Ko is vice president of the Samsung Electronics Design Technology Team.  He is responsible for all memory design methodology activities for the Samsung memory division, and also manages the relationships between memory division and EDA vendors. A 21-year veteran at Samsung, Ko’s expertise includes development of SDRAM, DDR, DDR2, DDR3, LPDD2, LPDDR3 and LPDDR4 devices. His internal honors include the Proud Samsung Award, the Jang Young-sil Award, and the Memory Award.

 

Landen and Ko were approved by a vote of the Si2 board, which represents leading semiconductor manufacturers and foundries, fabless companies, and EDA software providers.

Qualcomm and Samsung are active members of the Si2 OpenAccess and Compact Model Coalitions. OpenAccess is a standard application programming interface and reference source code for the design database used by all major chip design software suppliers. It provides end-user chip designers with inter-tool interoperability. Si2 standard, compact SPICE simulation models selected and supported by the Compact Model Coalition are used by every major circuit simulator in the semiconductor industry.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. Its activities include support of OpenAccess, the world’s most widely used standard API and reference database for integrated circuit design. All Si2 activities are carried out under the auspices of the The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.