IEEE Approves New Power Modeling Standard. 2416-2019 Built on Si2 Unified Power Model

AUSTIN, Texas–Silicon Integration Initiative has announced that its Unified Power Model, developed with major contributions from IBM and GLOBALFOUNDRIES, has been approved as IEEE 2416-2019, a new Standard for Power Modeling to Enable System Level Analysis, which complements UPF/IEEE 1801-2018 Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems.

Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

UPM/IEEE 2416-2019 provides a rich set of power modeling semantics enabling system designers to model entire systems with great flexibility. It supports power modeling from abstract design description all the way to gate level implementation providing data consistency from earliest architectural explorations to final power verification.

“We view UPM/IEEE 2416 as a major step forward for low power design,” commented Dr. Nagu Dhanwada of IBM, chair of the IEEE 2416 and the Si2 UPM Working Groups.

“The foundation of the UPM/IEEE 2416-2019 standard originated in IBM and has been successfully used in power sign-off of several generations and families of IBM microprocessors. Concepts like multi-level, state-based modeling and efficient, expressive semantics in UPM/IEEE 2416-2019 support constructing accurate and standardized power models for IP blocks. This enables SoC designs to be energy efficient from the ground up, a key reason companies will use 2416-2019 to upgrade modeling, analysis and sign-off flows,” stated Dr. Dhanwada.

Si2 UPM is a product of the Si2 OpenStandards Coalition, an R&D incubator which rapidly seeds and prototypes potential new EDA software tool interoperability standards. “The target of this development and subsequent standardization was an efficient and flexible mechanism for the specification and interchange of consistent power models throughout a project’s lifetime, from system design to manufacturing, especially for IP blocks and chiplets,” said Jerry Frenkil, Si2 director of OpenStandards. “This work led to significant advances in power modeling, including contributor and multi-level modeling, both of which are included in the 2416-2019 standard.”

A prototype power tool, upmPowerCalc, was built to prove the new concepts from end-to-end, both accelerating the delivery of a ready-to-implement standard and providing OpenStandards members with tools to aid in their own implementation.” The Si2 work was supported by the UPM Working Group consisting of ANSYS, IBM, Intel, Cadence, Entasys, and Thrace Systems.

Power contributors are Process, Voltage, and Temperature independent proxies for power. This PVT independence enables the late binding of PVT conditions at simulation run time, enabling power analysis at various PVT corners without requiring new libraries. Multi-level models provide multiple model views, or interfaces, to access the same power data. With multi-level construction, a single model provides consistent data for both system-level abstract simulations and bit-level simulations with RTL or gates.

“These advancements, along with UPM’s semantic expressiveness, deliver multiple benefits for design organizations” Frenkil explained. “System architects and SoC designers can model entire systems at a variety of PVT points with great flexibility. Power can be modeled in UPM using scalars, tables, expressions, and contributors, as well as expressions referencing contributors.”

UPM’s expressiveness also provides major benefits for IP developers. The use of power contributors leads to significant productivity gains since far fewer models and libraries are needed with UPM’s PVT independence. In addition, the models are abstract black boxes – functionality cannot be reverse-engineered from the power models.

Model interoperability and consistency with UPF/IEEE 1801 were identified early on as key goals in support of increasing emphasis on system level design. “IEEE 2416 provides a standardized interoperable system-level power model that is an essential piece of the foundation of an emerging industry-scale chiplet ecosystem” commented Ramune Nagisetty, senior principal engineer and director of Process and Product Integration at Intel Corporation.

“Energy-aware, system-level design can be a challenging task,” added John Biggs, chair of the IEEE P1801 Working Group, and distinguished engineer and co-founder of Arm. “With this new standard, designers will be better enabled by having access to semiconductor IP delivered with both IEEE 1801 power state models and IEEE 2416 power data models.”

For design automation groups, UPM provides an industry-standard format for both internal and external IP. This common format saves resources and time as there is no need to support or translate external proprietary formats. UPM also reduces reliance on internal proprietary formats, a long-standing design obsolescence trap.

An EDA startup, Thrace Systems, is planning to add IEEE 2416 support to its products. “UPM/IEEE 2416 is an important new standard. Its rich modeling semantics provide our power analysis platform with the solid infrastructure needed for comprehensive system level analysis,” commented David Ratchkov, Thrace Systems founder and CEO.

The P2416 Working Group was led by IBM, Si2, and Cadence, with active support from Intel and Arm.

For more information contact Jerry Frenkil at jfrenkil@si2.org.

Rahul Goyal of Intel Re-elected Board Chair of Silicon Integration Initiative

AUSTIN, Texas — Rahul Goyal of Intel has been reelected to a one-year term as board chair of Silicon Integration Initiative, a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. The election was held during Si2’s board meeting at the recent Design Automation Conference.

Other companies represented on the Si2 board are: ANSYS, Cadence Design Systems, GLOBALFOUNDRIES, Google, IBM, Qualcomm Technologies, Samsung, Siemens–a Mentor Business, Synopsys and Texas Instruments.

John Ellis, Si2 president and CEO, said Goyal’s reelection “will assure leadership continuity as we expand support for our members into such advanced technologies as artificial intelligence, machine learning, and design in the cloud.”

A member of the Si2 board since 2003, Goyal is vice president, Technology and Manufacturing Group and director, Research and Development Strategic Enabling for Intel. He has global responsibility for strategic sourcing, supply chain strategy, industry relations, ecosystem development, strategic collaborations, data analytics, and capacity management related to product development across Intel’s broad product portfolio. This includes software, system and semiconductor intellectual property, product development outsourcing services, electronic measurement solutions, Electronic Design Automation software, prototyping and verification products used in all aspects of product design, validation and technology development.

Goyal joined Intel in 1989 and has held various technical and management positions in software engineering and technology development. His previous roles there include engineering director in the Design and Technology Solutions Group, director of the integrated silicon technology roadmap development in the Microprocessor Products Group, and senior engineering manager of mask operations. Goyal holds a bachelor’s degree in electrical and electronics engineering from Birla Institute of Technology and Science in Pilani, India, and a master’s degree in computer engineering from Syracuse University in New York.

Si2 Elects Board Members for 2019-2020

Silicon Integration Initiative, a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools, announced today the election of the 2019-2020 board of directors. Board members will be introduced at the Si2 Member Meeting and Reception during the Design Automation Conference, June 3, 4:00 – 5:30 p.m., Las Vegas Westgate Hotel, Ballroom F.

Joining the Si2 Board this year is:

  • ANSYS—Vic Kulkarni, vice president and Chief Strategist, ANSYS Inc.

Re-elected board members are:

  • Cadence Design Systems—Stanley Krolikoski, fellow, Strategic Alliances
  • GLOBALFOUNDRIES—Richard Trihy, vice president, Design Enablement
  • Google—Roger Carpenter, Hardware Engineer
  • IBM—Leon Stok, vice president, Electronic Design Automation Technologies
  • Intel—Rahul Goyal, vice president, Technology and Manufacturing Group and director, Research and Development Strategic Enabling
  • Mentor, a Siemens Business—Mick Tegethoff, director of Product Marketing for Analog/Mixed-Signal/RF IC Verification Solutions
  • Qualcomm Technologies—Udi Landen, vice president of Engineering
  • Samsung Electronics—Seungbum Ko, vice president, Electronics Design Technology Team
  • Synopsys—David DeMaria, vice president, Corporate Marketing
  • Texas Instruments—Keith Green, distinguished member of the technical staff, Analog Technology Development

Details on the Si2 Member Meeting and Reception and other Si2 DAC activities are available at http://www.si2.org/dac_2019/

James Masters of Intel to Lead Si2 Extensions Steering Group

AUSTIN, Texas — James Masters of Intel has been elected chairman of the Silicon Integration Initiative Extensions Steering Group, a team of industry volunteers that creates productivity enhancements to OpenAccess, the world’s most widely used standard API and reference database for integrated circuit design. Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

The ESG was launched in 2011 to increase the ease and pace of adding OpenAccess functionality, through extensions to the database, without affecting the consistency and stability of the core API standard and its associated reference implementation.

Marshall Tiner, Si2 director of Production Standards, said the ESG is responsible for reviewing and approving new features and capabilities for the API which are not part of the regular development process. “This has allowed for more flexible development in the OpenAccess environment to meet ever-changing market requirements,” Tiner said.

“James has played a major role in the ESG since its creation. His work with Si2 is an example of his decade-long advocacy for standards to streamline the design flow and maximize productivity and reuse,” Tiner added. “That includes guidance developing the ESG’s major subgroups, oaScript and oaxPop. oaScript provides scripting-language access into the database for Python, tcl, Ruby, and perl, allowing rapid development of user-created tools. oaxPop is the polygon operators extension that makes use of oaScript to provide a Python-based, rapid polygon analysis package for users.”

A 23-year Intel veteran, Masters currently manages an Intel team that enables custom layout capabilities of process nodes, including development of process design kit content. He works with EDA suppliers to improve the overall custom layout of the EDA ecosystem.

Si2 Names Dr. Rhett Davis Technical and Education Advisor

AUSTIN, Texas — Rhett Davis, professor of Electrical and Computer Engineering at North Carolina State University, has been named Technical and Educational Advisor for Silicon Integration Initiative. Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

“This new position expands Davis’ reach and impact on the semiconductor industry,” said John Ellis, Si2 president and CEO.  “His experience with the Si2 OpenAccess database and in artificial intelligence and machine learning will be brought to bear on expanding the ecosystem surrounding our newly upgraded version of OA. The new OA release will greater support high-performance, partitioned, multithreaded AI EDA applications. Dr. Davis’ expertise will assist Si2 and its members in bridging the gap between visionary research and real-world, high-performance, AI applications.”

In this expanded advisory role Davis, who has a doctorate in electrical engineering from the University of California at Berkeley, will continue consulting for Si2 in the areas of system-level power modeling and compact modeling. He has been instrumental in prototyping early-stage implementation of the newly created Unified Power Model now being standardized by Si2 within IEEE.  In the Si2 Compact Model Coalition, Davis has helped the Open Model Interface Working Group rearchitect the TSMC-contributed interface, which allows users to modify model parameters during circuit simulation.

Davis will also support the five university members of the OpenAccess Coalition: North Carolina State, University of Florida, State University of New York, Stanford University and Einhoven University of Technology (Netherlands.)  University members have direct use of the OpenAccess database, which streamlines the path to developing design production tools.

Dr. Davis joined North Carolina State University in 2002 as an assistant professor and became professor in 2008. He received the National Science Foundation Faculty Early Career Development award in 2007 and the Si2 Distinguished Service Award in 2012 development of standards for electronic design automation, and the FreePDK open-source, predictive process design kit.

He has been an IEEE member since 1993 and became a senior member in 2011. He has published over 50 scholarly journal and conference articles

Dr. Davis’ research is centered on developing methodologies, CAD tools, and circuits for systems-on-chip in emerging technologies. His interests include 3DIC design and low-power and high-performance circuit design for digital signal-processing and embedded systems.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. Its activities include support of OpenAccess, the world’s most widely used standard API and reference database for integrated circuit design. All Si2 activities are carried out under the auspices of the The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws

Si2 Welcomes New Members: Mythic and Thrace Systems

Si2 welcomes its newest members

OpenAccess Coalition — Mythic
www.mythic-ai.com

 

 

OpenStandards Coalition — Thrace Systems
www.thracesystems.com

Qualcomm, Samsung Name New Si2 Board Members

AUSTIN, Texas—Qualcomm Incorporated and Samsung Electronics have named two executives to join the Silicon Integration Initiative board of directors.  Si2 is a global research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

Udi Landen is Vice President of Engineering at Qualcomm Technologies, Inc.  In his current role, Landen provides technical, management and business leadership for engineering teams at various international sites that focus on mobile and computing design enablement and CAD methodology automation roadmaps.  Prior to joining Qualcomm in 2013, Landen held executive and leadership roles at Altera Corp., Mercury Interactive and Cadence Design Systems.  He is a graduate of the Technion, Israel Institute of Technology.

 

Seungbum Ko is vice president of the Samsung Electronics Design Technology Team.  He is responsible for all memory design methodology activities for the Samsung memory division, and also manages the relationships between memory division and EDA vendors. A 21-year veteran at Samsung, Ko’s expertise includes development of SDRAM, DDR, DDR2, DDR3, LPDD2, LPDDR3 and LPDDR4 devices. His internal honors include the Proud Samsung Award, the Jang Young-sil Award, and the Memory Award.

 

Landen and Ko were approved by a vote of the Si2 board, which represents leading semiconductor manufacturers and foundries, fabless companies, and EDA software providers.

Qualcomm and Samsung are active members of the Si2 OpenAccess and Compact Model Coalitions. OpenAccess is a standard application programming interface and reference source code for the design database used by all major chip design software suppliers. It provides end-user chip designers with inter-tool interoperability. Si2 standard, compact SPICE simulation models selected and supported by the Compact Model Coalition are used by every major circuit simulator in the semiconductor industry.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. Its activities include support of OpenAccess, the world’s most widely used standard API and reference database for integrated circuit design. All Si2 activities are carried out under the auspices of the The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

 

Dr. Leigh Anne Clevenger Joins Si2 Technical Team

Machine Learning Expert Will Bolster Collaborative R&D Programs

Dr. Leigh Anne Clevenger, a professional software engineer with over 15 years’ experience at IBM and GlobalFoundries, has joined Si2 as a principal software design engineer.

With domain knowledge ranging from circuit simulation to data science, Dr. Clevenger will initially focus her expertise on accelerating the Si2 OpenStandards Coalition standardization efforts in machine learning and system-level power modeling.

Dr. Clevenger, who earned her doctorate in Software Engineering and Machine Learning at Pace University, has extensive experience in semiconductor design automation and semiconductor processing technology.  She is a published expert in detailed circuit simulator systems, including IBM PowerSPICE, Cadence Spectre/APS/XPS/Ultrasim, and Synopsys HSPICE.  At GlobalFoundries she was a software development engineer for automotive and gaming computer chips.

“Dr. Clevenger is known for driving business success through establishing collaboration and dialogue between all sectors of the electronic design automation and semiconductor communities,” said John Ellis, Si2 president and CEO.  “Her expertise in machine learning will be especially valuable to Si2 members who increasingly utilize that science to gain insights from data to improve the quality and efficiency of production and decision software systems.”

Dr. Clevenger has published and presented research on data science, including big data analytics, machine learning algorithms, and wearable computing.  She has filed over 30 patents in the areas of health care and fitness based on Internet of Things sensors, improving engagement with virtual and augmented reality and semiconductor innovations. For her doctorate, she developed a machine learning system for active screening of cardiac patients.

 

IBM, GLOBALFOUNDRIES Enhance Si2 Unified Power Model Standard

Si2 has announced  that IBM and GLOBALFOUNDRIES have contributed patented technology to support the Si2 Unified Power Model standard, the industry’s first significant power model enhancement in many years.

Early stage estimation of System on Chip power consumption is fundamental to ensuring new SoC designs meet or exceed power specifications when fabricated. For a credible estimate, the power models must comprehend the target implementation technology and circuitry, along with voltage and temperature conditions. At the same time, power estimation results are needed quickly in to perform rapid “what if” scenarios.

UPM’s multi-level power modeling capability provides the necessary level of modeling detail required at various stages of design. Abstract high-level equations to gate-level characterization tables can be accommodated through the same, standard interface. Beyond this, the UPM interface, upon acceptance and approval by the IEEE’s P2416 working group, will be a direct plug-in to the widely-used IEEE 1801 stub created for power models.

Simplified Power Modeling

The IBM and GF contributions enhance UPM by providing a new and unique approach to power modeling. Rather than storing pre-characterized, process-voltage-temperature specific data, UPM models store power proxies that represent different contributors to overall power consumption, such as sub-threshold leakage, gate leakage, and dynamic power. Appropriately entitled “power contributors,” this approach vastly simplifies and reduces the power modeling effort, and allows the power model to be voltage and temperature independent, enabling a single power model to be used at a multitude of voltages and temperatures.

SoC designers using UPM with contributor-based modeling will ultimately be equipped with thermally-aware, system-level power estimation. In addition, the late-binding of specific PVT conditions at simulation run-time will provide accurate, early estimates of leakage power, which increases exponentially with increasing temperature. The donated technology covers key aspects of contributor-based power modeling including model abstraction, generation, compression and evaluation.

Contributor-based modeling will be fully integrated into UPM, which forms the basis for P2416, the planned IEEE standard for developing and maintaining interoperable, IC design power models.  P2416 is scheduled for balloting in early 2019.

Industry Contributions

Jerry Frenkil, director of Si2 OpenStandards, said the IBM and GF contributions bolster UPM and provide P2416 with proven and ready-to-use modeling methods.  “These power proxies enable voltage and temperature-independent modeling which greatly reduce the model generation and support effort,” Frenkil explained. “They also enable late binding of voltage and temperature conditions at simulation run-time, a major benefit for both IP developers and SoC designers.”

“IBM is pleased to donate this advanced modeling technology to Si2’s UPM development to facilitate interchange of IP power data,” said Dr. Leon Stok, vice president of EDA at IBM.  “We have used contributor modeling internally on several generations of IBM micro-processors to great effect. We look forward to seeing UPM contributor models being provided by IP block developers so that entire systems, consisting of both internal and external IP, can be modeled efficiently using a common modeling standard.  Additionally, the combination of power contributors and multi-level modeling structures promises major cost and resource improvements in creating and supporting IP power models.”

“UPM directly addresses a major industry need—accurate and efficient system-level power models,” said Richard Trihy, senior director of design enablement at GF.  “Since IP providers need only produce a single model for a multitude of PVT points, these models enable significant productivity gains in model generation. Our clients will also get a good early estimate of their systems’ total power, including leakage, which can operate at high temperatures.”

Ready for P2416 Balloting

“These contributions from IBM and GF come at a fortuitous time,” said Dr. Nagu Dhanwada of IBM, chair of the IEEE P2416 Working Group and the Si2 UPM development project.  “The P2416 Working Group is rapidly gathering momentum towards IEEE standardization.  We anticipate going to ballot early next year.”

For more information about this project, contact Jerry Frenkil at jfrenkil@si2.org.  For information about the Low Power Working Group and other OpenStandards programs, visit http://www.si2.org/openstandards/.