Dr. Leigh Anne Clevenger Joins Si2 Technical Team

Machine Learning Expert Will Bolster Collaborative R&D Programs

Dr. Leigh Anne Clevenger, a professional software engineer with over 15 years’ experience at IBM and GlobalFoundries, has joined Si2 as a principal software design engineer.

With domain knowledge ranging from circuit simulation to data science, Dr. Clevenger will initially focus her expertise on accelerating the Si2 OpenStandards Coalition standardization efforts in machine learning and system-level power modeling.

Dr. Clevenger, who earned her doctorate in Software Engineering and Machine Learning at Pace University, has extensive experience in semiconductor design automation and semiconductor processing technology.  She is a published expert in detailed circuit simulator systems, including IBM PowerSPICE, Cadence Spectre/APS/XPS/Ultrasim, and Synopsys HSPICE.  At GlobalFoundries she was a software development engineer for automotive and gaming computer chips.

“Dr. Clevenger is known for driving business success through establishing collaboration and dialogue between all sectors of the electronic design automation and semiconductor communities,” said John Ellis, Si2 president and CEO.  “Her expertise in machine learning will be especially valuable to Si2 members who increasingly utilize that science to gain insights from data to improve the quality and efficiency of production and decision software systems.”

Dr. Clevenger has published and presented research on data science, including big data analytics, machine learning algorithms, and wearable computing.  She has filed over 30 patents in the areas of health care and fitness based on Internet of Things sensors, improving engagement with virtual and augmented reality and semiconductor innovations. For her doctorate, she developed a machine learning system for active screening of cardiac patients.

 

IBM, GLOBALFOUNDRIES Enhance Si2 Unified Power Model Standard

Si2 has announced  that IBM and GLOBALFOUNDRIES have contributed patented technology to support the Si2 Unified Power Model standard, the industry’s first significant power model enhancement in many years.

Early stage estimation of System on Chip power consumption is fundamental to ensuring new SoC designs meet or exceed power specifications when fabricated. For a credible estimate, the power models must comprehend the target implementation technology and circuitry, along with voltage and temperature conditions. At the same time, power estimation results are needed quickly in to perform rapid “what if” scenarios.

UPM’s multi-level power modeling capability provides the necessary level of modeling detail required at various stages of design. Abstract high-level equations to gate-level characterization tables can be accommodated through the same, standard interface. Beyond this, the UPM interface, upon acceptance and approval by the IEEE’s P2416 working group, will be a direct plug-in to the widely-used IEEE 1801 stub created for power models.

Simplified Power Modeling

The IBM and GF contributions enhance UPM by providing a new and unique approach to power modeling. Rather than storing pre-characterized, process-voltage-temperature specific data, UPM models store power proxies that represent different contributors to overall power consumption, such as sub-threshold leakage, gate leakage, and dynamic power. Appropriately entitled “power contributors,” this approach vastly simplifies and reduces the power modeling effort, and allows the power model to be voltage and temperature independent, enabling a single power model to be used at a multitude of voltages and temperatures.

SoC designers using UPM with contributor-based modeling will ultimately be equipped with thermally-aware, system-level power estimation. In addition, the late-binding of specific PVT conditions at simulation run-time will provide accurate, early estimates of leakage power, which increases exponentially with increasing temperature. The donated technology covers key aspects of contributor-based power modeling including model abstraction, generation, compression and evaluation.

Contributor-based modeling will be fully integrated into UPM, which forms the basis for P2416, the planned IEEE standard for developing and maintaining interoperable, IC design power models.  P2416 is scheduled for balloting in early 2019.

Industry Contributions

Jerry Frenkil, director of Si2 OpenStandards, said the IBM and GF contributions bolster UPM and provide P2416 with proven and ready-to-use modeling methods.  “These power proxies enable voltage and temperature-independent modeling which greatly reduce the model generation and support effort,” Frenkil explained. “They also enable late binding of voltage and temperature conditions at simulation run-time, a major benefit for both IP developers and SoC designers.”

“IBM is pleased to donate this advanced modeling technology to Si2’s UPM development to facilitate interchange of IP power data,” said Dr. Leon Stok, vice president of EDA at IBM.  “We have used contributor modeling internally on several generations of IBM micro-processors to great effect. We look forward to seeing UPM contributor models being provided by IP block developers so that entire systems, consisting of both internal and external IP, can be modeled efficiently using a common modeling standard.  Additionally, the combination of power contributors and multi-level modeling structures promises major cost and resource improvements in creating and supporting IP power models.”

“UPM directly addresses a major industry need—accurate and efficient system-level power models,” said Richard Trihy, senior director of design enablement at GF.  “Since IP providers need only produce a single model for a multitude of PVT points, these models enable significant productivity gains in model generation. Our clients will also get a good early estimate of their systems’ total power, including leakage, which can operate at high temperatures.”

Ready for P2416 Balloting

“These contributions from IBM and GF come at a fortuitous time,” said Dr. Nagu Dhanwada of IBM, chair of the IEEE P2416 Working Group and the Si2 UPM development project.  “The P2416 Working Group is rapidly gathering momentum towards IEEE standardization.  We anticipate going to ballot early next year.”

For more information about this project, contact Jerry Frenkil at jfrenkil@si2.org.  For information about the Low Power Working Group and other OpenStandards programs, visit http://www.si2.org/openstandards/.

Si2 Releases New Version of OpenAccess Design Database

Silicon Integration Initiative, an electronic design automation software research and development joint venture, has released Data Model 6, the newest version of OpenAccess, the world’s most widely used standard API and reference database for integrated circuit design.

DM6 is the first major OpenAccess revision since 2014. The OpenAccess database provides EDA software tools with immediate design flow interoperability, saving time and money for semiconductor designers and manufacturers. Innovative DM6 features will improve performance in both new and legacy applications.

Marshall Tiner, Si2 director of Production Standards, said DM6 can help the industry keep pace with design requirements for emerging artificial intelligence and machine learning applications. “As with all OpenAccess releases, DM6 is a production-quality, proven, stable design platform. It’s uniquely positioned to meet the new complexity and performance challenges facing IC designers.”

A key feature of DM6 is oaPartitions, which enables OpenAccess applications to access critical components of enormous designs as easily as opening much smaller designs, saving compute resources and allowing developers to start doing meaningful work faster. “The real power of DM6 comes from the new partitioning capability. By subdividing a complex design, OpenAccess provides simultaneous access to multiple partitions from separate processes. Applications can use oaPartitions to exploit the full compute power available on the user’s platform,” Tiner said.

With properly written applications taking advantage of the new data model, oaPartitions can customize how and what data will be loaded into memory from the database. Multiple simultaneous, unique applications can each be assigned their own partition, opening up a wide range of opportunities to accelerate the design flow on ever-growing, complex designs.

“The industry is looking for enablers for utilizing vast cloud-based hardware with multiple processors. oaPartitions provides just that,” Tiner said.

John Ellis, Si2 president and CEO, underscored the benefits of OpenAccess. “Use of OpenAccess API, source code, and scripting capability accelerates EDA vendor’s time to market, and provides users with tool-to-tool interoperability for optimal design flows. Without OA compatibility, time-consuming translations in and out of a vendor or user internally developed software tools are usually required, wasting some of the productivity gains a tool provides. Any software tool used for real-world, physical design that is not utilizing OA is at a serious disadvantage. The high-performance, partitioning capability of OA DM6 underscores the competitive advantage and power of OpenAccess.”

The OpenAccess Coalition is the governing body that manages the OpenAccess infrastructure. Cadence  Design Systems, Inc. contributed the OpenAccess API to Si2 in 2002 and serves as the co-architect of the Si2 Change Team that manages modifications to the API and data model. Cadence also provides Si2 and its OpenAccess Coalition members with rights to use their production-quality, reference implementation of the latest API and data model. DM6 is now available to all coalition members.

For more information about OpenAccess and Data Model 6, contact Marshall Tiner at mtiner@si2.org.

 

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. Si2’s international membership includes semiconductor foundries, fabless manufacturers and EDA companies.

 

In Memoriam: Eric Leavitt

Si2 and the EDA industry lost a friend and colleague with the recent passing of Eric Leavitt.

Eric was an EDA pioneer, starting at Digital Equipment Corporation in 1978 and later at Cadence Design Systems and Synopsys, Eric left his mark on many EDA products, and was a leader in the development of Si2 OpenAccess.

A Celebration of Life gathering will be held for Eric on Saturday, October 13, at 10 a.m. at Darling & Fischer – Chapel of the Hills in Los Gatos, Ca.

In lieu of flowers, a college fund has been set up for Eric’s son Jeff, at Bank of America, Account # 325116651248 (Yanfang Cao) or via Zelle 4083980824.

Google Joins Si2 Board of Directors

Google Joins Si2 Board of Directors

Election Reflects Growing Influence of Vertical Integration in IC Design

For Immediate Release

AUSTIN, Texas – Roger Carpenter, a Google hardware engineer with 30 years of experience in electronic design automation and chip design, has been elected to the Silicon Integration Initiative board of directors. Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

Before joining Google, Carpenter held executive roles at three EDA firms: Magma Design Automation, Javelin Design Automation and Envis. His design experience includes positions at Wave Computing, Broadcom, Chromatic Research and Xilinx. A holder of more than a dozen patents, Carpenter received a Bachelor’s and Master’s of Electrical Engineering and Computer Science from the Massachusetts Institute of Technology.

John Ellis, Si2 president and CEO, said that Google’s membership on the Si2 board reflects the increasing impact of vertical integration in the electronics industry. “A recent Si2 industry survey showed that over 80 percent of our end users develop some specialized, internal design tools. This proprietary software meets their unique needs and performance requirements,” Ellis said.

“Directly accessing the Si2 OpenAccess data base by making use of our Application Programming Interface, designers and integrators have greater control over their bottom line by optimizing their design flow and, in turn, shortening product time-to-market. It’s critical that system houses like Google, along with their unique semiconductor design software needs, are now represented on the Si2 board.”   The twelve members of the Si2 board represent leading semiconductor manufacturers and foundries, fabless companies, and EDA software providers.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

Rahul Goyal of Intel Elected Board Chair of Silicon Integration Initiative

AUSTIN, Texas — Rahul Goyal of Intel has been elected to a one-year term as board chair of Silicon Integration Initiative, a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. The election was held during Si2’s board meeting at the recent Design Automation Conference.

A member of the Si2 board since 2003, Goyal is vice president, Technology and Manufacturing Group and director, Research and Development Strategic Enabling for Intel. He has global responsibility for strategic sourcing, supply chain strategy, industry relations, ecosystem development, strategic collaborations, data analytics, and capacity management related to product development across Intel’s broad product portfolio. This includes software, system and semiconductor intellectual property, product development outsourcing services, electronic measurement solutions, Electronic Design Automation software, prototyping and verification products used in all aspects of product design, validation and technology development.

Goyal joined Intel in 1989 and has held various technical and management positions in software engineering and technology development. His previous roles there include engineering director in the Design and Technology Solutions Group, director of the integrated silicon technology roadmap development in the Microprocessor Products Group, and senior engineering manager of mask operations. Goyal holds a bachelor’s degree in electrical and electronics engineering from Birla Institute of Technology and Science in Pilani, India, and a master’s degree in computer engineering from Syracuse University in New York.

About Si2

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. The Si2 international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.

Si2 Elects Board Members for 2018-19

Si2 Elects Board Members for 2018-19

For Immediate Release

AUSTIN, Texas–Silicon Integration Initiative (Si2), a global research and development joint venture focused on developing and maintaining design software tool interoperability standards, announced today the election of the 2018-19 board of directors. Board members will be introduced at the Si2 Member Meeting and Reception during the Design Automation Conference (DAC), June 25, 4:00 p.m.-6:00 p.m., Marriott Marquis Hotel, Sierra Room B.

Joining the Si2 Board for the first time is:

  • Jose Corleto, vice president, Engineering, Qualcomm Technologies, Inc. (NASDAQ:QCAM)

Re-elected board members are:

  • David DeMaria, vice president, Corporate Marketing, Synopsys
  • Keith Green, distinguished member of the technical staff, Analog Technology Development, Texas Instruments
  • Rahul Goyal, vice president, Technology and Manufacturing Group and director, Research and Development Strategic Enabling, Intel Corp.
  • Jong-Bae Lee, vice president,  Design Technology Team, Samsung Electronics
  • Leon Stok, vice president,  Electronic Design Automation Technologies, IBM
  • Humair Mandavia, Chief Strategy Officer, Zuken, Inc.
  • Stanley Krolikoski, fellow, Strategic Alliances, Cadence Design Systems
  • Richard Trihy, Senior Director, Design Enablement, GLOBALFOUNDRIES
  • Mick Tegethoff, director of Product Marketing for Analog/Mixed-Signal/RF IC Verification Solutions, Mentor, a Siemens Business

Details on the Si2 Member Meeting and Reception and other Si2 DAC activities are available at http://www.si2.org/dac-2018/

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. The Si2 international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.

Contact:

Silicon Integration Initiative
Terry Berke
512-917-1358
tberke@si2.org

Si2 to Demonstrate System-Level Unified Power Model and Power Tool at DAC 2018

Si2 to Demonstrate System-Level Unified Power Model and Power Tool at DAC 2018


New Standard and Prototype Tool Estimate and Control IC Power Consumption

AUSTIN, Texas —Silicon Integration Initiative (Si2), an Austin-based integrated circuit research and development joint venture, will demonstrate its Unified Power Model (UPM), a newly developed system-level power modeling standard, and accompanying prototype tool at DAC 2018 in San Francisco. The Si2 standard and tool help designers estimate and control power consumption at the system level, abilities widely identified as critical requirements in meeting product power constraints.

Demonstrations will be held at the Moscone Center, Tuesday, June 26 and Wednesday, June 27, 11:00 a.m. and 2:00 p.m., Booth 1338.

UPM focuses on the system level and provides model consistency across different abstractions, from systems down to gates. Multiple data representations—expressions, multi-dimensional tables, and scalars—provide modeling flexibility. Voltage and temperature independent modeling greatly reduce the model generation and support effort, and enable the late binding of voltage and temperature conditions at simulation run-time.

“UPM is a flexible power modeling standard that facilitates interchange of IP power data, while providing several benefits like reduced model generation effort and costs, and enablement for early, accurate system level power estimates,” said Dr. Nagu Dhanwada of IBM, chair of the Si2 UPM project and the IEEE P2416 working group. UPM is the primary source for the emerging IEEE P2416 standard.

Jerry Frenkil, director of Si2 Open Standards, said UPM was developed to address low-power design issues at the system level. “For IP developers, the rich set of power modeling semantics supports IP macro abstraction and provides flexibility for a variety of modeling approaches.  For SoC designers, UPM’s temperature and voltage sensitive models enable thermally aware, system-level power estimation, vastly improving early analysis and quality of results,” Frenkil said.  “For EDA developers, UPM provides standardized compatibility with UPF/IEEE1801 and opportunities for new applications based upon UPM’s unique features.

“UPM has the additional benefit of industry and academic oversight, as the Si2 Low Power Working Group members—ANSYS, Cadence, Entasys, IBM, Intel and North Caroline State University (NCSU)—oversaw the development,” added Frenkil.  “NCSU’s involvement follows Si2’s long standing practice of partnering with Universities and Professors for collaborative R&D”.

The modeling language and prototype tool using that language, were developed in parallel.  Si2 designed and built a prototype system-level power estimator, PowerCalc, which natively uses the UPM IP models.  Additionally, PowerCalc was built from the ground up with support for multi-processing and cloud computing. This parallel development of the modeling standard and a compatible tool was a major factor in refining the model structure and enabling efficient model execution.

Si2 plans to contribute the latest UPM specification to the IEEE P2416 Standards Working Group for industry-wide standardization and distribution.  “Since Si2 is an R&D joint venture, our members can work together collaboratively, with anti-trust protection, to develop advanced technology, including specifications, prototypes, and reference designs.  Our work on UPM provides P2416 with a proven and ready to use model interface,” Frenkil added.

For more information about this project, contact Jerry Frenkil at Jfrenkil@si2.org.  For information about the Low Power Working Group and other OpenStandards programs, visit http://www.si2.org/openstandards/.

Founded in 1988, Si2 is a leading research and development joint ventures that provides standard interoperability solutions for integrated circuit design tools.  All Si2 activities are carried out under the auspices of the the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. Si2’s international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.

 

Contact

Terry Berke
512-917-1358
tberke@si2.org

 

Take the OpenAccess Voice of Customer Survey

Help us find ways to improve Si2 OpenAccess, the world’s most widely used, open reference database for IC design, with a supporting standard API.  This three-minute survey provide insights members of the OpenAccess Coalition will use to bolster design-tool interoperability in the coming years.

Si2 Open Model Interface Provides Industry-Wide Standard for Advanced SPICE Capabilities

AUSTIN, Texas–The Silicon Integration Initiative Compact Model Coalition has released the Open Model Interface, an Si2 standard, C-language application programming interface that supports SPICE compact model extensions.OMI allows circuit designers to simulate and analyze such important physical effects as self-heating and aging, and perform extended design optimizations. It is based on TMI2, the TSMC Model Interface, which was donated to Si2 by TSMC in 2014. OMI supports four of CMC’s 13 SPICE models:

  • BSIM (Berkeley Short-channel IGFET Model)-BULK, a Bulk MOSFET model that provides excellent accuracy compared to measured data in all regions of operation.
  • BSIM-CMG (Common Multi-Gate), a compact model for the class of common multi-gate FETs. All of today’s important Multi-Gate (MG) transistor behaviors are captured by this model.
  • HiSIM2 (Hiroshima-university STARC IGFET Model), one of the early adopters of the surface potential model compared to the traditional Vt extraction based models
  • BSIM-SOI (Silicon-On-Insulator) a model formulated on top of the BSIM framework which accurately captures the complex physics in silicon-on-insulator devices used in logic and RF applications.

Additional models will continue to be added by the CMC OMI Working Group.

CMC members include semiconductor manufacturers, circuit designers, and simulation tool providers. They pool resources to fund and develop SPICE standard compact models and standard interfaces to promote IC design interoperability. As a publicly available Si2 standard API, OMI can be downloaded at no charge. CMC members have unique access to QA test benches to certify OMI implementation in their software tools.

The public version of OMI, which includes documentation, the API description, and example code is available at http://www.si2.org/cmc

“OMI allows for modeling of device degradation over time, which is referred to as aging, and provides for statistical modeling of process variations,” said John Ellis, Si2 president. “For the most advanced designs, OMI adds to the SPICE flexibility by encapsulating the modeling-layout-dependent efforts of complex structures. New features on top of the SPICE models can be added, such as safe operating area checks.

Colin Shaw, senior applications engineer at Silvaco and chair of the OMI Working Group, stated, “The effort to create an industry standard involved the contributor, TSMC, along with over 40 individuals from CMC member companies. This new release of OMI expands TMI2’s original capability to support of other key models, and is poised to streamline the designer’s optimization capability, as the ability to modify device parameters is standardized by foundries and simulation tool providers.”

Dr. Peter Lee, director at Micron Memory Japan and CMC chair, said,  “As OMI is adopted by foundries and integrated device manufacturers, its benefits and cost-effectiveness will grow. CMC members include leading developers who have committed to aligning their working group efforts with OMI. Through these efforts to increase industry standardization, members have a clear, competitive advantage with access to code and additional resources.”

About the Compact Model Coalition

Now in its 22nd year, the Si2 Compact Model Coalition provides semiconductor manufacturers, designers, and simulation tool providers a means to pool resources to fund standardization and optimization of standard compact (SPICE) models, and standard interfaces to promote simulation tool interoperability. CMC funds and supports select university and national laboratory compact model developers. The CMC quality assurance program ensures that simulations are accurate and uniform across different vendors. The world’s most advanced semiconductor designs are all designed and simulated using the standards funded by the CMC.

About the Silicon Integration Initiative (Si2)

Si2 is a leading research and development joint venture that provides standard interoperability solutions for IC design tools. Its primary products include OpenAccess, the world’s most widely used, open reference database for IC design, with a supporting standard APA. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.