Si2 Approves IC Design Simulation Standards for Gallium Nitride Devices

Si2 Approves Two IC Design
Simulation Standards for Fast-Growing
Gallium Nitride Market


Compact Model Coalition Models Expected to
Reduce Costs, Speed Time-to-Market

 

For Immediate Release

 

AUSTIN–The Silicon Integration Initiative’s (Si2) Compact Model Coalition (CMC) has approved two integrated circuit design simulation standards that target the fast-growing global market for gallium nitride semiconductors.

The approved standards are the 12th and 13th models currently funded and supported by the CMC, a collaborative group that develops and maintains cost-saving SPICE (Simulation Program with Integrated Circuit Emphasis) models for IC design.

John Ellis, president and CEO, said gallium nitride devices are used in many high-power and high-frequency applications, including satellite communications, radar, cellular, broadband wireless systems, and automotive. “Although it’s currently a small market, gallium nitride devices are expected to show remarkable growth over the coming years.”

To reduce research and developments costs and increase simulation accuracy, the semiconductor industry relies on the CMC to share resources for funding standard SPICE models. Si2 is a research and development joint venture focused on IC design and tool operability standards. “Once the standard models are proven and accepted by CMC, they are incorporated into design tools widely used by the semiconductor industry. The equations at work in the standard model-setting process are developed, refined and maintained by leading universities and national laboratories. The CMC directs and funds the universities to standardize and improve the models,” Ellis explained.

Dr. Ana Villamor, technology and market analyst at Yole Développement (Yole), Lyon, France, said that “2015 and 2016 were exciting years for the gallium nitride power business. We project an explosion of this market with 79% CAGR between 2017 and 2022. Market value will reach US $460 million at the end of the period1. It’s still a small market compared to the impressive US $30 billion silicon power semiconductor market,” Villamor said. “However, its expected growth in the short term is showing the enormous potential of the power gallium nitride technology based on its suitability for high performance and high frequency solutions.”

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Peter Lee, manager at Micron Memory Japan and CMC chair, said that “Gallium nitride devices are playing an increasingly important part in the field of RF and power electronics. With these two advanced models established as the first, worldwide gallium nitride model standards, efficiencies in design will greatly increase by making it possible to take into account accurate device physical behavior in design, and enabling the use of the various simulation tools in the industry with consistent results.”

Click here to download standard models.

 

About the Silicon Integration Initiative (Si2)

Si2 is a leading research and development joint venture that provides standard interoperability solutions for IC design tools. Its primary products include OpenAccess, the world’s most widely used, open reference database for IC design, with a supporting standard APA. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

 

Media Contact:

Terry Berke
512-917-1358
tberke@si2.org

 

  1. Source: Power GaN 2017: Epitaxy, Devices, Applications, and Technology Trends report, Yole Développement, 2017

 


Developer Insights on Gallium Nitride Compact Models

“GaN HEMTs are widely used in power electronic systems and RF power applications, such as radar, wireless backhaul, and base transceiver stations for future high speed and high data rate communication systems. The recent standardization of GaN compact models will be the key enabler for these applications, which require the combination of an efficient foundry/fabless ecosystems.”

Yogesh Chauhan
Co-Developer, GaN ASM-HEMT Model
Associate Professor
IIT Kanpur, India

 


“Advance circuit simulations are a must for optimal, time- and cost-effective use of gallium nitride devices. Device modeling is the heart of circuit simulations, and the “Advance SPICE Model for GaN” (ASM GaN) has been developed after years of rigorous research. This model has been meticulously tested through the CMC process and is a turn-key solution for gallium nitride-based circuit design. I believe ASM GaN will enable design of leading-edge gallium nitride-based products.”

Sourabh Khandelwal
Co-Developer, GaN ASM-HEMT Model
Assistant Professor
Macquarie University
Sydney, Australia

 


“The MIT Virtual Source GaN-HEMT (MVSG) model distills the key physics in the operation of gallium nitride, high-electron-mobility transistors in a numerically robust form to facilitate accurate and meaningful circuit simulations.  Gallium nitride-based product designs in that utilize such physics-based compact models will stand to gain critical insights on device behavior within the system and will save on design overhead.”

Ujwal R. Krishna
Developer, GaN-MVSG Model
Postdoctoral Research Associate
Massachusetts Institute of Technology
Cambridge, Mass.

 

Jushan Xie New Vice-Chair of Si2 Compact Model Coalition

Dr. Jushan Xie, senior software architect at Cadence Design Systems, is the new vice-chair of the Si2 Compact Model Coalition. He joined Cadence in January 1999, working with SPICE (Simulation Program with Integrated Circuit Emphasis) model extraction tools and later SPICE modeling for circuit simulation. He is currently in charge of Spectre SPICE modeling and reliability modeling. He received a Ph.D. in Physics from University of Saarland, Saarbruecken, Germany, in 1996, and a second Ph.D. in applied mathematics from Louisiana Tech University, in 1999.

The Si2 Compact Model Coalition is a collaborative group that develops and maintains cost-saving SPICE models for IC design.

Empyrean Software, Qorvo Join Si2 Compact Model Coalition

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Empyrean Software, Qorvo Join Si2 Compact Model Coalition

 

For Immediate Release

 

AUSTIN, Texas—Empyrean Software and Qorvo have joined the Silicon Integration Initiative (Si2) Compact Model Coalition (CMC), a collaborative group that funds the standardization of cost-saving SPICE models for integrated circuit designs.

They join 30 other companies that increasingly rely on the use of industry-standard SPICE models (Simulation Program with Integration Circuit Emphasis) to simulate the performance of new and enhanced chip designs prior to manufacturing. As a research and development joint venture focused on IC design tool operability standards, Si2 provides a legally protected environment for its members to share resources for funding SPICE model standardization.

“SPICE device models are equations that express transistor function. These fundamental building blocks provide IC designers with the ability to simulate and validate design function and performance before entering the capital-intensive phase of manufacturing,“ said John Ellis, Si2 president and CEO. “To reduce R&D costs and increase simulation accuracy, the semiconductor industry has turned to the CMC to pool resources and fund the standardization of best-of breed models.

“Once the standard models are proven and accepted by CMC, they are incorporated into design tools providing cross-correlation between simulators and widely used by the semiconductor industry. The standard models have been developed, and are refined and maintained, under direction and funding by the CMC, by leading universities and national labs,” Ellis explained.

Steve Yang, CEO of Empyrean Software, said “As designs move to advanced processes, the simulation models provided by CMC are vitally important for our tools to provide accurate results and validate designs before they are manufactured.  As the largest China EDA software supplier, Empyrean’s EDA tools cover complete custom AMS design flow: schematic entry, layout editing, circuit simulation, DRC/LVS, and RC extraction.”

For more information about the CMC visit http://www.si2.org/cmc/.

 

About the Silicon Integration Initiative (Si2)

Si2 is a leading research and development joint venture that provides standard interoperability solutions for IC design tools. Its primary products include OpenAccess, the world’s most widely used, open reference database for IC design, with a supporting standard APA. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws.

 

Media Contact:

Terry Berke
512-917-1358
tberke@si2.org

Challenges and Opportunities in Global Standardization of Compact Models

DAC 2016

The Si2 Compact Model Coalition (CMC) is a collaborative industry-academia organization for creating standards for SPICE compact models. CMC standards drive innovation across the semiconductor foundry-fabless ecosystem by ensuring that well-vetted compact models and compact model interfaces are consistently implemented in vendor circuit simulators. This panel discusses developing cutting-edge models while simultaneously improving/maintaining legacy models and acting in the presence of a challenging model developer funding climate. Special focus is on models currently in the CMC pipeline including GaN, HEMTs (gallium nitride high-electron mobility transistors) and electrostatic discharge protection devices.

What you will learn

  • Advantages of using industry-wide compact model standards

  • New compact models in development and significant changes to legacy models

  • Challenges and solutions in evolving model language descriptions

  • How the CMC helps individual companies succeed and innovate

  • The status of R&D funding status and its impact on compact model development

Panelists

  • Moderator: John Ellis, President and CEO, Si2

  • Rob Jones, Senior Principal Engineer at Raytheon, Microelectronics Engineering & Technology Group, Raytheon

  • Marek Mierzwinski, Research and Development Engineer, Keysight Technologies

  • Josef Watts, Principal Member of the Technical Staff, GLOBALFOUNDRIES

  • Richard Williams, IBM

  • Peter Lee, Manager, Micron Technology

GaN HEMT SPICE Model Standard for Power and RF

Description:

Si2’s Compact Model Coalition is currently in the third phase of our process to define a standard model for GalliumNitride (GaN) High Electron-Mobility Transistors (HEMTs). These devices are currently used in high power switching and RF applications, where their power and speed sets them apart from most other technologies. We started with eight candidates, which have been down-selected to two remaining candidates, based on a set of technical requirements. In the current phase, member companies are asked to perform their own evaluations hopefully leading to a standard in 2016.

Bio:

Samuel Mertens is working for Cadence Design Systems on the Spectre circuit simulator, after working at Ansoft, Ansys, Agilent and Keysight. He has been an active representative at the CMC since 2004, having chaired the CMC’s Standard Spice Language standard. Samuel graduated with a Physics Engineering (BS) degree from the University of Gent (Belgium) and the MS and PhD in Electrical Engineering and Computer Sciences from Massachusetts Institute of Technology (Cambridge, MA).

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Geoffrey Coram Named New CMC Technical Advisor

Geoffrey J. Coram of Analog Devices is the new volunteer technical advisor for the Si2 Compact Model Coalition.  In this newly created position he advises the coalition on Verilog-A implementation for its standard compact models.

Over the past decade, the preferred language for development and implementation of compact models has shifted from C to Verilog-A. Recognizing the importance of the new language, the CMC officers created this position to assist model developers and help encourage best practices.

A senior member of the IEEE, Geoffrey has been an active CMC participant since 2002 and currently leads the CMC subcommittees on Verilog-A recommended practices and the MOS varactor model. In 2004, he led the efforts of the Accellera Verilog-AMS subcommittee to add compact modeling extensions to that modeling language in Language Reference Manual version 2.2.

Geoffrey joined the internal CAD development and circuit simulation group at Analog Devices after earning a Ph.D. from the Massachusetts Institute of Technology in 2000. His undergraduate degree is from Rice University.