System level co-design of chip, package and PCB using native design databases in a unified 3D cockpit

Author:  James Church

Today’s advanced packaging design requires low layer count and high pin density to satisfy the cost pressures facing the electronics industry. By leveraging the native design formats, rules and technologies of each substrate designers can achieve a cohesive, optimized and properly constrained product.

Combining the OpenAccess IC layout database and Zuken’s own Package/PCB database format into a single hierarchically linked 3D system, enables system level optimization and visualization for a top-down or bottom-up flow that is not achievable in discrete point tools.

This paper was voted “Best Paper” by an audience survey taken after every presentation.


Chip/Package/Board Co-Design and Co-Analysis: Moving from Spreadsheets to EDA

DAC 2016:


SoC development has become more than just silicon design. Today, successful SoC design requires consideration of the electrical, thermal, and mechanical interactions of the chip, the package and the board. This is especially true for silicon-in-package designs and 3D designs such as Hybrid Memory Cubes and High Bandwidth Memories. Co-design of the silicon and the package has become essential. This panel will present and discuss different challenges with and approaches to co-design and co-analysis.

What you will learn

  • Recent developments in 3D and co-design

  • Challenges and solutions in automating co-design and co-analysis

  • Applications most in need of co-design and co-analysis


  • Moderator, Jerry Frenkil, Director of OpenStandards, Si2

  • Humair Mandavia, Chief Strategy Officer, Zuken

  • Brandon Wang, Group Director, Cadence Design Systems

  • Teresa McLaurin, ARM