Chip/Package/Board Co-Design and Co-Analysis: Moving from Spreadsheets to EDA

DAC 2016:


SoC development has become more than just silicon design. Today, successful SoC design requires consideration of the electrical, thermal, and mechanical interactions of the chip, the package and the board. This is especially true for silicon-in-package designs and 3D designs such as Hybrid Memory Cubes and High Bandwidth Memories. Co-design of the silicon and the package has become essential. This panel will present and discuss different challenges with and approaches to co-design and co-analysis.

What you will learn

  • Recent developments in 3D and co-design

  • Challenges and solutions in automating co-design and co-analysis

  • Applications most in need of co-design and co-analysis


  • Moderator, Jerry Frenkil, Director of OpenStandards, Si2

  • Humair Mandavia, Chief Strategy Officer, Zuken

  • Brandon Wang, Group Director, Cadence Design Systems

  • Teresa McLaurin, ARM


CHIP – PACKAGE CO – DESIGN ( OPEN3D ) Membership Agreement

Membership in the Si2 Chip-Package Co-Design (aka (Open3D))  requires agreement to the following documents.



Second:  DTMC__DFMC__Operating_Policy-1.pdf:  Attachment C- Project IP Policy