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Low Power Workshop   Low Power Workshop


Dates:      October 5, 2006
Venue:   
SEMI Headquarters, Click on each presentation to view

Low Power Workshop Abstract:
Low power design has been identified as a critical area for design flow improvement in the 65nm regime and beyond. This workshop, lasting a day, is intended to serve as an open forum for key contributors from EDA and end-user companies to identify the critical needs in the area of low power  design, verification and analysis of integrated circuit chips. The goal is to first assimilate requirements from a varied group of presenters from end-user design companies representing requirements to satisfy the needs of microprocessor, SoC and AMS chip designs. Subsequent discussions will be held among the participants at the workshop to enlist the work content and responsibilities, and to identify the specific areas (language extensions, library standards, design constraints, flow interfaces, etc) where standards need to be created or extended to enable an open environment for more advanced low power design flows and capabilities.

Agenda:
09:00am - 09:10am: Introduction,  John Ellis, SEMI and Steve Schulz, Si2

09:10am - 09:40am: Keynote Address,  Unifying the Industry behind a Power Format Standard:
David Peterman, Texas Instruments

09:40am – 011:40pm: Session 1,  User Requirements for Low Power SoC Design
•    Presentations on flow requirements for power management, characterization and implementation challenges for low power SoC/ASIC designs

SoC Flow Requirements for Power Management: Mika Naula, Nokia

Power characterization, power management, and design data communications requirements supporting the Consumer and Storage Industries: Gary Delp, LSI Logic

Implementation challenges designing with Multiple Supply Voltages: Herve Menager, NXP

DSM Power Management, Overview and Requirements: Lew Chua-Eoan, Qualcomm
11:40am – 012:10pm: Break and Working Lunch

12:10pm – 01:10pm: Session 2,  User Requirements for Low Power Library/IP Design
•    Presentations on low power design flow requirements from the viewpoint of library and IP producers
ARM Presentation:  Rob Aitken, John Goodenough
Virage Presentation: Oscar Siguenza
 
01:10am – 02:40pm: Session 3,   User Requirements for Low Power Microprocessor Design
•    Presentations on flow requirements for low power microprocessor designs
ARM Presentation: Dave Flynn, John Goodenough
AMD presentation: Gil Watt
Power Estimation @ Sun: Rob Mains

02:40am – 02:55pm: Break

02:55am – 04:40pm: Session 4: Interactive Session 1

•  Summarize flow needs & interface/standards requirements identified by end-user presentations
Interactively solicit feedback from industry audience and validate key points of summary
Propose “straw man” structure for prototypical flows & unified standards to meet needs posed by audience

04:40am – 04:55pm: Break

04:55am – 05:50pm: Session 5: Interactive Session 2

•  Discuss planned standards development process and responsibilities
  Agree on early target dates
•  List key initial leaders / participants  

05:50am – 06:00pm: Concluding Remarks: Shrenik Mehta

Link to EE Times article on the Low Power Workshop


 
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