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 Si2 Board of Directors

Board Listed Alphabetically by Company
Advanced Micro Devices
Kalyan Thumaty
Senior Director, Design Engineering

Kalyan Thumaty serves as a Senior Director, Design Engineering at AMD responsible for CAD and Methodology. Mr. Thumaty is an accomplished engineering and business leader with a proven track record at Semiconductor and EDA companies, particularly in the areas of design methodology and implementation. Mr. Thumaty previously served as vice president and general manager at Cadence Design Systems and as vice president of applications engineering and services at Simplex Solutions prior to its acquisition by Cadence.

Mr. Thumaty's prior experience includes business development and services management positions at Cadence Design Systems and design management positions at Synergy Semiconductor. Mr. Thumaty holds a M.S.E in electrical engineering from the Arizona State University and B.E in biomedical engineering from Osmania University, India.

Dr. John Goodenough
VP, Design Technology and Automation

John Goodenough has been involved in silicon design and EDA tools and methods for the past twenty years. He is currently the World Wide Director of Design Technology for ARM. In this role he has strategic and budgetary responsibility for ARM's internal Design Automation infrastructure. In addition he is responsible to work with ARM's product definition and research teams to define the technology roadmap for the integration of IP design views in Customer flows. Working across all of ARM's divisional engineering and product definition gives John a unique perspective into the issues of both the design of IP and SoC components in a large multinational enterprise and the problems faced creating viable business oriented interoperability standards.

In addition to serving as an Si2 Board Member for the last several years, John is a founding director of the SPIRIT Consortium for IP reuse and overseas ARM's involvement in other industry design automation standards efforts such as Accelera OSCI and VSIA. With a diverse background and recent direct experience closely related to the Si2 mandate, John contributes strongly to the development and promotion of useful EDA standards. Dr Goodenough holds a BSc in Engineering Science from the University of Durham and a PhD in VLSI Architecture from the University of Sheffield both in the United Kingdom.

Cadence Design Systems, Inc.
Tom Beckley
Senior Vice President, Custom IC & PCB Group

Tom Beckley is senior vice president of the Custom IC & PCB Group. His product responsibilities include the Virtuoso® design environment, physical design and routing, and simulation product lines for full-custom digital and analog design. He is also responsible for infrastructure such as the OpenAccess database, the process design kits (PDKs) that are essential for physical IC design, and for the Allegro® and OrCAD® design and routing, and Sigrity™ high-speed analysis solutions for printed circuit boards and IC packaging.

In addition, Beckley is an executive sponsor of the Cadence Quality Initiative, a sustained corporate focus on developing and deploying processes enabling design, implementation and delivery of high-quality, full-featured products. Beckley joined Cadence in 2004 via the acquisition of Neolinear, where he served as President and CEO. Neolinear developed innovative auto-interactive and automated analog/RF tools and solutions for mixed-signal design. Prior to Neolinear, Beckley was head of the Systems Division at Avant! Corporation. He came to Avant! through the acquisition of Xynetix Design Systems, the market leader in advanced IC packaging and systems-level virtual prototyping, where he was President and CEO. Prior to Xynetix, Beckley held engineering and management positions at Harris Corporation and General Motors. Beckley received his BS in mathematics and physics from Kalamazoo College and an MBA from Vanderbilt University.

Dr Leon Stok
Vice President of EDA

Leon Stok is currently Vice President of EDA at IBM and is responsible for delivering and supporting productive and effective design methodologies for all IBM design teams. This group develops design tools and design methods and provides both tools and supports experts to the entire silicon and system design community. Leon has a vision to take the CAD industry to platform level and sees a crucial role for Si2 to play in this evolution.

Prior to this he held positions as Director of EDA, Executive Assistant to IBM's Senior Vice President of Technology and Intellectual Property and executive assistant to IBM’s Senior Vice President of the Technology group.

Leon Stok has been involved in the research and development of EDA tools for the past twenty years. After developing high-level and logic synthesis (BooleDozer) tools, he initiated and led the development of PDS, IBM's placement driven synthesis tool. Following that he led the research and development of logic, physical, simulation and manufacturing tools at IBM's research division.

Leon Stok studied electrical engineering at Eindhoven University of Technology, the Netherlands, from which he graduated with honors in 1986. He obtained a Ph.D. degree from Eindhoven University in 1991. Leon Stok worked at IBM's Thomas J. Watson Research Center as part of the team that developed BooleDozer, the IBM logic synthesis tool. Subsequently he managed IBM's logic synthesis group, and lead all of IBM's design automation research as the Senior Manager Design Automation at IBM Research from 1999-2004.

Dr. Stok has published over fifty papers on many aspects of high level, architectural and logic synthesis, low power design, placement driven synthesis and on the automatic placement and routing for schematic diagrams. He was elected an IEEE fellow for the development and application of high-level and logic synthesis algorithms.

With a diverse background and a passion to develop efficient design platforms, Leon Stok continues to contribute strongly to the development and promotion of useful EDA standards.

Intel Corporation
Rahul Goyal
Vice President, Technology and Manufacturing Group Director, Electronic Design Automation Business

Rahul Goyal is responsible for Intel's strategic engagements with the EDA industry. His team drives Intel's EDA strategy, supplier engagements, strategic equity investments in design & CAD, standards development with industry consortia, and university research in design sciences.

Rahul has been with Intel for over 24 years, and has held several technical and management positions in software engineering and technology development. Prior to joining Intel, Rahul was a design engineer.

Rahul is a member of the board of directors of Silicon Integration Initiative (Si2). He has also served as chairman of Design Technology Council (DTC), an industry think tank, and as an observer on the board of directors of several Intel Capital portfolio companies. Rahul holds a Masters degree in Computer Engineering from Syracuse University, and a Bachelor's degree (with honors) in Electrical Engineering from BITS, Pilani, in India.

Mentor Graphics Corporation
Pravin Madhani
General Manager, Place and Route Division

Pravin Madhani is the General Manager of the Place and Route Division of Mentor Graphics and brings more than 21 years of experience in EDA industry. Prior to Mentor, he was Founder, President and CEO of Sierra Design Automation. Sierra was a venture-backed startup in the area of deep-submicron place & route tools. Sierra's Olympus-SoC Place and Route platform features a unique, patented architecture specifically created to address variability and design closure for extremely large and complex IC designs. Sierra was acquired by Mentor Graphics Corporation in 2007. Prior to Sierra, Mr. Madhani was Founder, President and CEO of Everest Design Automation. Everest designed patented gridless toplevel routing technology for large system on-Chip designs. Everest was acquired by Synopsys in 1998. Mr. Madhani has also held various positions in R&D with Silicon Graphics/MIPS EDA division and LSI Logic EDA division where he worked in the area of timing analysis and routing software development.

Mr. Madhani received his Masters degree in Computer Engineering from the University of Texas at Austin and his Bachelors degree in Electrical Engineering from the Indian Institute of Technology, Bombay, India.

Chairman of the Si2 Board of Directors
Qualcomm Technologies, Inc
Nick Yu
VP, Engineering

Nick Yu is a Vice President of Engineering at Qualcomm's CDMA Technologies Division. He is currently responsible for setting Qualcomm's semiconductor technology roadmaps including wafer fab process node, backend interconnect and packaging technologies. He manages engineering teams that are involved with our supply chain partners on execution of the technology roadmaps for Qualcomm's chipset solutions.

Nick has 20 years of experience with Qualcomm on low power wireless chipset and SoC development, including managing chipset design, advanced semiconductor technology, deep submicron circuit design and methodology development , advanced semiconductor R&D and packaging development. He is one of the architects of, and has participated in the definition and development of, many Qualcomm chipset products. Nick has an MSEE degree from Georgia Institute of Technology.

Samsung Electronics
Sungho Park,
Sr. Vice President

Sungo Park is the Sr. Vice President of AP Development at System LSI Division of Samsung Electronics. Sungho joined Samsung Electronics in 1996 to participate in the 21264 Alpha CPU develop with Digital Equipment Corporation in Hudson Massachusetts. In 1998, he moved to API Networks, a private company funded by Samsung and Compaq, to continue work on Alpha CPU system chip development. Later on in 2002, he moved to System LSI division in Korea as VP of Engineering responsible for development of Network processors, MCU and ASIC products. Since 2007, he headed the AP Development, responsible for development of high performance mobile AP SoC products including the S3C6410, S5C110, and the latest Exynos series. Prior to Samsung Electronics, he worked on development of PowerPC 603, 7xx at IBM, Sparc based MCU at Fujitsu Microelectronics and various SoCs at AMD, Intel and Mostek.

Sungho graduated with a BSEE in 1980 from Georgia Institute of Technology and an MSEE in 1984 from University of Illinois at Chicago.

Philippe Magarshack
Exec VP, Design Enablement and Services

Philippe Magarshack has been the Executive Vice-President, Design Enablement and Services at ST since September, 2012. In this role, Magarshack manages the Central ST activities for PDKs, Design Flows, EDA vendor strategy, Libraries and Physical IP Development and sourcing. Magarshack is also in charge of the teams implementing the first SoCs on new technology nodes, recently in 28nm FD-SOI and now 14nm, as well as CPU/GPU hardening. Magarshack is ST's Enablement Executive at the IBM ISDA Technology Alliance for the development of advanced CMOS process.

From 1985 to 1989. Magarshack worked as a microprocessor designer at AT&T Bell Labs in New Jersey and California. In 1989, he joined Thomson-CSF in Grenoble, France, and took responsibility for libraries and ASIC design flows for the military market. In 1994, Magarshack joined SGS-THOMSON, where he held several roles in CAD and Libraries management for advanced CMOS processes.

In 2005, Magarshack was promoted to Group Vice President and General Manager of Central CAD and Design Solutions at STMicroelectronics' Technology R&D and Manufacturing organization.

Synopsys, Inc
Karen Bartleson
Sr. Director of Corporate Programs and Initiatives

Karen Bartleson has 30 years' experience in semiconductors and EDA. She is Senior Director of Corporate Programs and Initiatives at Synopsys. Her responsibilities include driving industry standards, EDA interoperability, customer engagement, higher education, and research. She was CAD manager at UTMC and logic analysis manager at Texas Instruments.

Ms. Bartleson served on numerous committees that create and govern standards. She was a member of the boards of OVI and VI simultaneously during the Verilog-VHDL “language wars”. She previously represented Synopsys on the Board of Directors of Si2.

Ms. Bartleson is President of the IEEE Standards Association; her term ends December 31, 2014. IEEE-SA produces global standards, developed by more than 20,000 individuals. Karen chairs IEEE-SA's Board of Governors which provides financial oversight and establishes policy. She is a member of the Board of IEEE which steers the business of the world's largest professional society. She is a member of the Strategic Planning Committee of both IEEE-SA and the IEEE.

Karen holds a BSEE from Cal Poly SLO and received the 2003 Women in Design Automation Achievement Award. She is author of “The Ten Commandments for Effective Standards” book. She has published numerous articles about standards and governance and is a contributing technical expert to Electronic Design magazine.

Ms. Bartleson's extensive experience makes her uniquely qualified to represent Synopsys, the EDA industry, and its customers on Si2's Board of Directors. Her service to the industry demonstrates her advocacy, and that of Synopsys, for an open environment that customers demand.

John Ellis
President & CEO

John Ellis was named President and CEO of Si2 in February 2015. John had served Si2 as Vice President of Engineering. John has more than 25 years of experience leading diverse research and development programs spanning multiple industries. After graduating from the University of Texas with a Master's in Mechanical Engineering, John worked at Sandia National Labs, where he focused on R&D projects for the Department of Energy, Department of Defense, National Institute of Standards and Technology, and other federal agencies. His experience includes nuclear weapons testing, missile guidance, air-borne and space-borne imaging systems, Internet and IC security, and semiconductor manufacturing.

In 2000, John's career took him to SEMI, a global trade association for the semiconductor industry, where as VP of Technology was responsible for global semiconductor manufacturing standards as well as coordination of industry initiatives such as e-Diagnostics and 450mm wafer size economics analyses.

Suk Lee
Senior Director of Design Infrastructure Marketing

Suk Lee has over 25 years of experience in the Semiconductor, EDA, and IP industries and is currently Senior Director of Design Infrastructure Marketing Division at TSMC. He has held engineering, marketing, and senior management positions at LSI Logic, Texas In- struments, Cadence, and Magma Design Systems.

Suk Lee holds a Bachelor of Engineering from MIT and Master of Science from the University of Toronto.

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