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  April 3, 2014

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DFMC Introduction

Design for Manufacturability Coalition (DFMC) Introduction

Design for Manufacturability design flows have become increasingly critical as normal excursions in semiconductor manufacturing result in significant variations for yield, power and performance at 45 nm process nodes and below. Both Process limited yield (PLY) and Circuit limited yield (CLY). lower manufacturing profits since these circuits must be scrapped or sold at a discount because they miss the power and/or performance targets of a nominal device.

In response to these issues, the Design for Manufacturability Coalition (DFMC) has developed a standard interface format that describes a comprehensive set of
DFM parameters that can verify that a circuit will meet it’s profit targets. The DFM parameters are defined in an open-source and extensible standard format called
OpenDFM which provides a common set of DFM parameters to a wide variety of physical verification and analysis tools dramatically improving the interface between EDA vendors and
silicon foundries.

Plans for 2012 include: OpenDFM 2.x to include DRC+ and other enhancements, OPEX 1.0 to include
open parasitic extraction parameters, and a new standard, OpenLVS, to cover LVS.

Major Accomplishments - 2011

  • OpenDFM 1.1 Physical Verification standard released, including ESD (Electro Static Discharge) and Latch Up Checks, Edge Operations and Edge Checks, and new Targeting
    Functions that will improve manufacturability
  • Completed proof-of-concept and development of OPEX 1.0 specification to be released as a standard in 2012
  • DRC+ contributed to accelerate next-generation standard in DRC pattern recognition

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