Si2 Elects Board Members for 2018-19

Si2 Elects Board Members for 2018-19

For Immediate Release

AUSTIN, Texas–Silicon Integration Initiative (Si2), a global research and development joint venture focused on developing and maintaining design software tool interoperability standards, announced today the election of the 2018-19 board of directors. Board members will be introduced at the Si2 Member Meeting and Reception during the Design Automation Conference (DAC), June 25, 4:00 p.m.-6:00 p.m., Marriott Marquis Hotel, Sierra Room B.

Joining the Si2 Board for the first time is:

  • Jose Corleto, vice president, Engineering, Qualcomm Technologies, Inc. (NASDAQ:QCAM)

Re-elected board members are:

  • David DeMaria, vice president, Corporate Marketing, Synopsys
  • Keith Green, distinguished member of the technical staff, Analog Technology Development, Texas Instruments
  • Rahul Goyal, vice president, Technology and Manufacturing Group and director, Research and Development Strategic Enabling, Intel Corp.
  • Jong-Bae Lee, vice president,  Design Technology Team, Samsung Electronics
  • Leon Stok, vice president,  Electronic Design Automation Technologies, IBM
  • Humair Mandavia, Chief Strategy Officer, Zuken, Inc.
  • Stanley Krolikoski, fellow, Strategic Alliances, Cadence Design Systems
  • Richard Trihy, Senior Director, Design Enablement, GLOBALFOUNDRIES
  • Mick Tegethoff, director of Product Marketing for Analog/Mixed-Signal/RF IC Verification Solutions, Mentor, a Siemens Business

Details on the Si2 Member Meeting and Reception and other Si2 DAC activities are available at http://www.si2.org/dac-2018/

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the The National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. The Si2 international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.

Contact:

Silicon Integration Initiative
Terry Berke
512-917-1358
tberke@si2.org

Si2 to Demonstrate System-Level Unified Power Model and Power Tool at DAC 2018

Si2 to Demonstrate System-Level Unified Power Model and Power Tool at DAC 2018


New Standard and Prototype Tool Estimate and Control IC Power Consumption

AUSTIN, Texas —Silicon Integration Initiative (Si2), an Austin-based integrated circuit research and development joint venture, will demonstrate its Unified Power Model (UPM), a newly developed system-level power modeling standard, and accompanying prototype tool at DAC 2018 in San Francisco. The Si2 standard and tool help designers estimate and control power consumption at the system level, abilities widely identified as critical requirements in meeting product power constraints.

Demonstrations will be held at the Moscone Center, Tuesday, June 26 and Wednesday, June 27, 11:00 a.m. and 2:00 p.m., Booth 1338.

UPM focuses on the system level and provides model consistency across different abstractions, from systems down to gates. Multiple data representations—expressions, multi-dimensional tables, and scalars—provide modeling flexibility. Voltage and temperature independent modeling greatly reduce the model generation and support effort, and enable the late binding of voltage and temperature conditions at simulation run-time.

“UPM is a flexible power modeling standard that facilitates interchange of IP power data, while providing several benefits like reduced model generation effort and costs, and enablement for early, accurate system level power estimates,” said Dr. Nagu Dhanwada of IBM, chair of the Si2 UPM project and the IEEE P2416 working group. UPM is the primary source for the emerging IEEE P2416 standard.

Jerry Frenkil, director of Si2 Open Standards, said UPM was developed to address low-power design issues at the system level. “For IP developers, the rich set of power modeling semantics supports IP macro abstraction and provides flexibility for a variety of modeling approaches.  For SoC designers, UPM’s temperature and voltage sensitive models enable thermally aware, system-level power estimation, vastly improving early analysis and quality of results,” Frenkil said.  “For EDA developers, UPM provides standardized compatibility with UPF/IEEE1801 and opportunities for new applications based upon UPM’s unique features.

“UPM has the additional benefit of industry and academic oversight, as the Si2 Low Power Working Group members—ANSYS, Cadence, Entasys, IBM, Intel and North Caroline State University (NCSU)—oversaw the development,” added Frenkil.  “NCSU’s involvement follows Si2’s long standing practice of partnering with Universities and Professors for collaborative R&D”.

The modeling language and prototype tool using that language, were developed in parallel.  Si2 designed and built a prototype system-level power estimator, PowerCalc, which natively uses the UPM IP models.  Additionally, PowerCalc was built from the ground up with support for multi-processing and cloud computing. This parallel development of the modeling standard and a compatible tool was a major factor in refining the model structure and enabling efficient model execution.

Si2 plans to contribute the latest UPM specification to the IEEE P2416 Standards Working Group for industry-wide standardization and distribution.  “Since Si2 is an R&D joint venture, our members can work together collaboratively, with anti-trust protection, to develop advanced technology, including specifications, prototypes, and reference designs.  Our work on UPM provides P2416 with a proven and ready to use model interface,” Frenkil added.

For more information about this project, contact Jerry Frenkil at Jfrenkil@si2.org.  For information about the Low Power Working Group and other OpenStandards programs, visit http://www.si2.org/openstandards/.

Founded in 1988, Si2 is a leading research and development joint ventures that provides standard interoperability solutions for integrated circuit design tools.  All Si2 activities are carried out under the auspices of the the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. Si2’s international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.

 

Contact

Terry Berke
512-917-1358
tberke@si2.org